參數(shù)資料
型號: P89LPC9402FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 60/60頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標準包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
9 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
P1.5/RST
11
I
P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O
ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force ISP mode.
P1.6
10
I/O
P1.6 — Port 1 bit 6. High current source.
P1.7
9
I/O
P1.7 — Port 1 bit 7. High current source.
P2.0 to P2.3,
P2.5
I/O
Port 2: Port 2 is an 5-bit I/O port with a user-congurable output type. During reset
Port 2 latches are congured in the input only mode with the internal pull-up disabled.
The operation of Port 2 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 7.14.1 “Port
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0
6
I/O
P2.0 — Port 2 bit 0.
P2.1
7
I/O
P2.1 — Port 2 bit 1.
P2.2/MOSI
18
I/O
P2.2 — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When congured as master, this pin is output; when
congured as slave, this pin is input.
P2.3/MISO
19
I/O
P2.3 — Port 2 bit 3.
I/O
MISO — When congured as master, this pin is input, when congured as slave, this
pin is output.
P2.5/SPICLK
20
I/O
P2.5 — Port 2 bit 5.
I/O
SPICLK — SPI clock. When congured as master, this pin is output; when congured
as slave, this pin is input.
P3.0 to P3.1
I/O
Port 3: Port 3 is a 2-bit I/O port with a user-congurable output type. During reset
Port 3 latches are congured in the input only mode with the internal pull-up disabled.
The operation of Port 3 pins as inputs and outputs depends upon the port conguration
selected. Each port pin is congured independently. Refer to Section 7.14.1 “Port
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described below:
P3.0/XTAL2/
CLKOUT
14
I/O
P3.0 — Port 3 bit 0.
O
XTAL2 — Output from the oscillator amplier (when a crystal oscillator option is
selected via the ash conguration.
O
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It
can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or
external clock input, except when XTAL1/XTAL2 are used to generate clock source for
the RTC/system timer.
P3.1/XTAL1
13
I/O
P3.1 — Port 3 bit 1.
I
XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
selected via the ash conguration). It can be a port pin if internal RC oscillator or
watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used
to generate the clock for the RTC/system timer.
SDA_LCD
63
I/O
SDA LCD — I2C-bus data signal for the LCD controller.
SCL_LCD
64
I/O
SCL LCD — I2C-bus clock signal for the LCD controller.
BP0 to BP3
27 to 30
O
BP0 to BP3: LCD backplane outputs.
Table 3.
Pin description …continued
Symbol
Pin
Type Description
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