參數(shù)資料
型號(hào): P89LPC9402FBD,557
廠商: NXP Semiconductors
文件頁數(shù): 35/60頁
文件大?。?/td> 0K
描述: IC 80C51 MCU FLASH 8K 64-LQFP
標(biāo)準(zhǔn)包裝: 450
系列: LPC900
核心處理器: 8051
芯體尺寸: 8-位
速度: 18MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LCD,LED,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
其它名稱: 935288631557
P89LPC9402_1
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 22 April 2009
40 of 60
NXP Semiconductors
P89LPC9402
8-bit microcontroller with accelerated two-clock 80C51 core
7.27.12 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive conguration. The BANK SELECT command can be used to load display data
in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector
functions are independent of the output bank selector.
7.27.13 Blinker
The LCD controller has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the BLINK command. Each blink frequency is a multiple
integer value of the clock frequency; the ratio between the clock frequency and blink
frequency depends on the blink mode selected, as shown in Table 9.
An additional feature allows an arbitrary selection of LCD segments to be blinked in the
static and 1:2 drive modes. This is implemented without any communication overheads by
the output bank selector which alternates the displayed data between the data in the
display RAM bank and the data in an alternative RAM bank at the blink frequency. This
mode can also be implemented by the BLINK command.
The entire display can be blinked at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
MODE SET command.
Blink modes 0.5 Hz, 1 Hz and 2 Hz, and nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz
correspond to an oscillator frequency (fosc(LCD)) of 1536 Hz at pin CLK. The oscillator
frequency range is 397 Hz to 3046 Hz.
7.27.13.1
I2C-bus controller
The LCD controller acts as an I2C-bus slave receiver. In the P89LPC9402 the hardware
subaddress inputs A0, A,1 and A2 are tied to VSS setting the hardware subaddress = 0.
7.27.14 Input lters
To enhance noise immunity in electrically adverse environments, RC low-pass lters are
provided on the SDA and SCL lines.
7.27.15 I2C-bus slave addresses
The I2C-bus slave address is 0111 0000. The LCD controller is a write-only device and will
not respond to a read access.
Table 9.
Blinking frequencies
Blink mode
Normal operating mode ratio
Normal blink frequency
Off
-
Blinking off
2 Hz
fosc(LCD)/768
2 Hz
1Hz
fosc(LCD)/1536
1 Hz
0.5 Hz
fosc(LCD)/3072
0.5 Hz
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