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參數(shù)資料
| 型號(hào)： | P89V52X2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 13/57頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標(biāo)準(zhǔn)包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱： | 568-4251-5 935282526112 P89V52X2FN |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
20 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.9.1 Capture mode
In the Capture mode there are two options which are selected by bit EXEN2 in T2CON. If
EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which
upon overowing sets bit TF2, the Timer 2 overow bit.
The capture mode is illustrated in Figure 14.
4
TCLK
Transmit clock ag. When set, causes the UART to use Timer 2
overow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overows to be used for the transmit clock.
3
EXEN2
Timer 2 external enable ag. When set, allows a capture or reload to
occur as a result of a negative transition on T2EX if Timer 2 is not
being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
2
TR2
Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.
1C/T2
Timer or counter select. (Timer 2)
0 = internal timer (fosc/6)
1 = External event counter (falling edge triggered; external clock’s
maximum rate = fosc/12
0
CP/RL2
Capture/Reload ag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overow.
Table 18.
T2MOD - Timer 2 mode control register (address C9H) bit allocation
Not bit addressable; Reset value: XX00 0000B
Bit
7
6
5
4
3
2
1
0
Symbol
-
T2OE
DCEN
Table 19.
T2MOD - Timer 2 mode control register (address C9H) bit description
Bit
Symbol
Description
7 to 2
-
Reserved for future use. Should be set to ‘0’ by user programs.
1
T2OE
Timer 2 Output Enable bit. Used in programmable clock-out mode
only.
0
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be congured
as an up/down-counter.
Table 17.
T2CON - Timer/Counter 2 control register (address C8H) bit description …continued
Bit
Symbol
Description
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| P89V660 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
| P89V660_0811 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI |
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