參數資料
| 型號： | P89V52X2FN,112 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 8/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 80C51 MCU FLASH 8K 40-DIP |
| 產品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 標準包裝： | 216 |
| 系列： | 89V |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | UART/USART |
| 外圍設備： | POR |
| 輸入/輸出數： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 192 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1012-ND - BOARD FOR P89V52X2 44-TQFP 622-1008-ND - BOARD FOR LPC9103 10-HVSON |
| 其它名稱： | 568-4251-5 935282526112 P89V52X2FN |
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P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
16 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
Table 11.
TMOD - Timer/Counter mode control register (address 89H) bit description
Bit
Symbol
Description
7
T1GATE
Gating control for Timer 1. When set, Timer/Counter is enabled only
while the INT1 pin is HIGH and the TR1 control pin is set. When
cleared, Timer 1 is enabled when the TR1 control bit is set.
6
T1C/T
Timer or Counter select for Timer 1. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T1 input pin).
5
T1M1
Mode select for Timer 1.
4
T1M0
3
T0GATE
Gating control for Timer 0. When set, Timer/Counter is enabled only
while the INT0 pin is HIGH and the TR0 control pin is set. When
cleared, Timer 0 is enabled when the TR0 control bit is set.
2
T0C/T
Timer or Counter select for Timer 0. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T0 input pin).
1
T0M1
Mode Select for Timer 0.
0
T0M0
Table 12.
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
M1
M0
Operating mode
0
8048 timer ‘TLx’ serves as 5-bit prescaler
0
1
16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
1
0
2
8-bit auto-reload Timer/Counter ‘THx’ holds a value
which is to be reloaded into ‘TLx’ each time it
overows.
1
3
(Timer 0) TL0 is an 8-bit Timer/Counter controlled
by the standard Timer 0 control bits. TH0 is an 8-bit
timer only controlled by Timer 1 control bits.
1
3
(Timer 1) Timer/Counter 1 stopped.
Table 13.
TCON - Timer/Counter control register (address 88H) bit allocation
Bit addressable; Reset value: 0000 0000B; Reset source(s): any reset
Bit
7
6
5
4
3
2
1
0
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 14.
TCON - Timer/Counter control register (address 88H) bit description
Bit
Symbol
Description
7
TF1
Timer 1 overow ag. Set by hardware on Timer/Counter overow.
Cleared by hardware when the processor vectors to Timer 1 Interrupt
routine, or by software.
6
TR1
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter
1 on/off.
5
TF0
Timer 0 overow ag. Set by hardware on Timer/Counter overow.
Cleared by hardware when the processor vectors to Timer 0 Interrupt
routine, or by software.
4
TR0
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter
0 on/off.
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