參數(shù)資料
型號(hào)： P89V52X2FN,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 6/57頁(yè)
文件大?。?/td> 0K
描述： IC 80C51 MCU FLASH 8K 40-DIP
產(chǎn)品培訓(xùn)模塊： Migrating from 8/16-Bit MCUs to 32-Bit ARMs
標(biāo)準(zhǔn)包裝： 216
系列： 89V
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： UART/USART
外圍設(shè)備： POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 192 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
配用： 622-1017-ND - BOARD 44-ZIF PLCC SOCKET
622-1012-ND - BOARD FOR P89V52X2 44-TQFP
622-1008-ND - BOARD FOR LPC9103 10-HVSON
其它名稱(chēng)： 568-4251-5
935282526112
P89V52X2FN
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
14 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.6 Reset
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins HIGH. Powering up the device
without a valid reset could cause the device to start executing instructions from an
indeterminate location. Such undened states may inadvertently corrupt the code in the
ash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held HIGH long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to VDD through a 10 F
capacitor and to VSS through an 8.2 k resistor as shown in Figure 9.
During initial power the POF ag in the PCON register is set to indicate an initial power-up
condition. The POF ag will remain active until cleared by software.
Following a reset condition, under normal conditions, the device will start executing code
from address 0000H in the user’s code memory. However if the requirements are met for
ICP entry, the device will enter ICP mode.
Table 9.
AUXR1 - Auxiliary register 1 (address A2H) bit description
Bit
Symbol
Description
7 to 4
-
Reserved for future use. Should be set to ‘0’ by user programs.
3
GF2
General purpose user-dened ag.
2
0
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
1
-
Reserved for future use. Should be set to ‘0’ by user programs.
0
DPS
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
Fig 9.
Power-on reset circuit
002aaa543
VDD
8.2 k
RST
XTAL2
XTAL1
C1
C2
10
F
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P89V660_08 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
P89V660_0811 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI
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