參數(shù)資料
型號(hào)： PCI1510ZVF
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 115/128頁
文件大?。?/td> 735K
代理商： PCI1510ZVF
65
Table 64. Socket Present-State Register (Continued)
BIT
SIGNAL
TYPE
FUNCTION
10
5VCARD
R
5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.
0 = 5-V VCC is not supported.
1 = 5-V VCC is supported.
Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an
invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the controller.
0 = Normal operation (default)
1 = Potential data loss due to card removal
9
BADVCCREQ
R
8
DATALOST
R
7
NOTACARD
R
Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not
updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
6
IREQCINT
R
READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface.
0 = READY(IREQ)//CINT low
1 = READY(IREQ)//CINT high
5
CBCARD
R
CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
4
16BITCARD
R
16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated
until another card interrogation sequence occurs (card insertion).
3
PWRCYCLE
R
Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as:
0 = Socket powered down (default)
1 = Socket powered up
2
CDETECT2
R
CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD2 low (PC Card may be present)
1 = CCD2 high (PC Card not present)
1
CDETECT1
R
CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD1 low (PC Card may be present)
1 = CCD1 high (PC Card not present)
0
CARDSTS
R
CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.
0 = CSTSCHG low
1 = CSTSCHG high
6.4
Socket Force Event Register
The socket force event register is used to force changes to the socket event register (CB offset 00h, see Section 6.1)
and the socket present-state register (see Section 6.3). Bit 14 (CVSTEST) in this register must be written when
forcing changes that require card interrogation. See Table 65 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket force event
CardBus socket address + 0Ch
Read-only, Write-only
0000 0000h
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