參數(shù)資料
型號： PCI1510ZVF
廠商： Texas Instruments, Inc.
英文描述： PC CARD CONTROLLERS
中文描述： PC卡控制器
文件頁數(shù)： 70/128頁
文件大?。?/td> 735K
代理商： PCI1510ZVF
410
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64-Kbyte page, and the
upper 16 bits (3116) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 312
are read/write. Bits 1 and 0 are read-only and always return 00b, forcing I/O windows to be aligned on a natural
doubleword boundary.
NOTE:
Either the I/O base register or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the
controller to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16
bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 152 are read/write and
allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 3116 of the appropriate
I/O base) on doubleword boundaries.
Bits 3116 are read-only and always return 0000h when read. The page is set in the I/O base register. Bits 1 and 0
are read-only and always return 00b, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The controller assumes that the lower 2 bits of the limit address are 11b.
NOTE:
The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
Default
31
0
30
0
29
0
28
0
27
0
26
0
25
0
24
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
0
Bit
Default
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Register:
Offset:
Type:
Default:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
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