參數(shù)資料
型號(hào): PCI1510ZVF
廠商: Texas Instruments, Inc.
英文描述: PC CARD CONTROLLERS
中文描述: PC卡控制器
文件頁數(shù): 47/128頁
文件大小: 735K
代理商: PCI1510ZVF
39
PCI1510
Application-
Specific Delay
Current Limiting
R
500
PCI1510
Current Limiting
R
500
LED
LED
Figure 37. Two Sample LED Circuits
As indicated, the LED signal is driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signals remain driven.
3.5.9
CardBus Socket Registers
The controller contains all registers for compatibility with the
PC Card Standard
. These registers exist as the CardBus
socket registers and are listed in Table 34.
Table 34. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
10h
Reserved
14h1Ch
Socket power management
20h
3.6
Serial-Bus Interface
The controller provides a serial-bus interface to load subsystem identification information and selected register
defaults from a serial EEPROM, and to provide a PC Card power-switch interface alternative. The serial-bus interface
is compatible with various I
2
C and SMBus components.
3.6.1
Serial-Bus Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the
appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4
terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (PCI offset
B3h, see Section 4.48) is set. The SBDETECT bit is cleared by a writeback of 1b.
The controller implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When
pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal
and the SDA signal is mapped to the MFUNC1 terminal. The controller drives SCL at nearly 100 kHz during data
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