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參數(shù)資料
| 型號： | PCI6515 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專用智能卡插槽 |
| 文件頁數(shù)： | 31/148頁 |
| 文件大?。?/td> | 760K |
| 代理商： | PCI6515 |
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215
Table 211. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
A_OE
K17
O
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during host
memory read cycles.
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that
supports DMA. The controller asserts OE to indicate TC for a DMA write operation.
A_READY
(IREQ)
E12
I
Ready. The ready function is provided when the 16-bit PC Card and the host socket are configured for the
memory-only interface. READY is driven low by 16-bit memory PC Cards to indicate that the memory card
circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC
Card is ready to accept a new data transfer command.
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a controller on the
16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is
requested.
A_REG
E13
O
Attribute memory select. REG remains high for all common memory accesses. When REG is asserted,
access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute
memory is a separately accessed section of card memory and is generally used to record card capacity and
other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card
that supports DMA. The controller asserts REG to indicate a DMA operation. REG is used in conjunction with
the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
A_RESET
C15
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
A_VS1
A_VS2
A13
B16
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine
the operating voltage of the PC Card.
A_WAIT
C12
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in
progress.
A_WE
G17
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for
memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as a TC during DMA operations to a 16-bit PC Card that supports DMA.
The controller asserts WE to indicate the TC for a DMA read operation.
A_WP
(IOIS16)
A11
I
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on
16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function.
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that
is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that
supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation.
Table 212. CardBus PC Card Interface System Terminals
SOCKET A TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
A_CCLK
F18
O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All
signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down
for power savings.
A_CCLKRUN
A11
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the controller to indicate that the CCLK frequency is going to be decreased.
A_CRST
C15
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known
state. When CRST is asserted, all CardBus PC Card signals are placed in a high-impedance state, and
the controller drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
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