參數(shù)資料
型號: PCI6515
廠商: Texas Instruments, Inc.
英文描述: SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述: 單插槽CardBus控制器,專用智能卡插槽
文件頁數(shù): 51/148頁
文件大小: 760K
代理商: PCI6515
317
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.29).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 312 describes the SMI control
bits function.
Table 312. SMI Control
BIT NAME
FUNCTION
SMIROUTE
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTAT
This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
SMIENB
When set, SMI interrupt generation is enabled.
The CSC interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control
register (ExCA offset 1Eh/81Eh, see Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC3 or MFUNC6 through the multifunction routing status register (PCI offset 8Ch, see Section 4.35).
3.8
Power Management Overview
In addition to the low-power CMOS technology process used for the PCI6515 controller, various features are
designed into the controller to allow implementation of popular power-saving techniques. These features and
techniques are as follows:
Clock run protocol
Cardbus PC Card power management
16-bit PC Card power management
Suspend mode
Ring indicate
PCI power management
Cardbus bridge power management
ACPI support
PCI Bus
PCI6515
EEPROM
Smart
Card
Power Switch
PC Card
Power Switch
The system connection to GRST is implementation-specific. GRST must be asserted on initial power up of the PCI6515 controller. PRST must
be asserted for subsequent warm resets.
Figure 312. System Diagram Implementing CardBus Device Class Power Management
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