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參數(shù)資料
| 型號： | PCI6515 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專用智能卡插槽 |
| 文件頁數(shù)： | 37/148頁 |
| 文件大?。?/td> | 760K |
| 代理商： | PCI6515 |
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33
a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus
target supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the
PCI Local Bus Specification
, and the issue is resolved by the PCI master using
LOCK.
3.4.3
Serial EEPROM I
2
C Bus
The PCI6515 controller offers many choices for modes of operation, and these choices are selected by programming
several configuration registers. For system board applications, these registers are normally programmed through the
BIOS routine. For add-in card and docking-station/port-replicator applications, the PCI6515 controller provides a
two-wire inter-integrated circuit (IIC or I
2
C) serial bus for use with an external serial EEPROM.
The PCI6515 controller is always the bus master, and the EEPROM is always the slave. Either device can drive the
bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on the
SCL and SDA signal lines. The PCI6515 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI6515 controller detects a logic-high level on the SCL terminal at the end of GRST, then it
initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I
2
C limit of 16 Kbits can
be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI6515 controller.
Figure 33 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI6515 I
2
C bus can be used to read and write from
other I
2
C serial devices. A system designer can control the I
2
C bus, using the PCI6515 controller as bus master, by
reading and writing PCI configuration registers
. Setting bit 3 (SBDETECT) in the serial bus control/status register (PCI
offset B3h, see Section 4.49) causes the PCI6515 controller to route the SDA and SCL signals to the SDA and SCL
terminals, respectively. The read/write data, slave address, and byte addresses are manipulated by accessing the
serial bus data, serial bus index, and serial bus slave address registers (PCI offsets B0h, B1h, and B2h; see Sections
4.46, 4.47, and 4.48, respectively).
EEPROM interface status information is communicated through the serial bus control and status register (PCI offset
B3h, see Section 4.49). Bit 3 (SBDETECT) in this register indicates whether or not the PCI6515 serial ROM circuitry
detects the pullup resistor on SCL. Any undefined condition, such as a missing acknowledge, results in bit 0
(ROM_ERR) being set. Bit 4 (ROMBUSY) is set while the subsystem ID register is loading (serial ROM interface is
busy).
The subsystem vendor ID for function 5 is also loaded through EEPROM. The EEPROM load data goes to both
functions from the serial EEPROM loader.
SCL
SDA
VCC
A0
A1
A2
SCL
SDA
PCI6515
Serial
ROM
Figure 33. Serial ROM Application
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| PCI6515ZHK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
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