參數(shù)資料
型號： PCI6515
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 83/148頁
文件大?。?/td> 760K
代理商： PCI6515
425
Table 414. Multifunction Routing Status Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
74
MFUNC1
RW
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
0000 = GPI1
0100 = OHCI_LED 1000 = CAUDPWM
0001 = GPO1
0101 = IRQ5
1001 = IRQ9
0010 = INTB
0110 = RSVD
1010 = IRQ10
0011 = IRQ3
0111 = RSVD
1011 = IRQ11
1100 = LEDA1
1101 = RSVD
1110 = GPE
1111 = IRQ15
30
MFUNC0
RW
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
0100 = IRQ4
1000 = CAUDPWM
0001 = GPO0
0101 = IRQ5
1001 = IRQ9
0010 = INTA
0110 = RSVD
1010 = IRQ10
0011 = IRQ3
0111 = RSVD
1011 = IRQ11
1100 = LEDA1
1101 = RSVD
1110 = GPE
1111 = IRQ15
One or more bits in this register are cleared only by the assertion of GRST.
4.36 Retry Status Register
The contents of the retry status register enable the retry time-out counters and display the retry expiration status. The
flags are set when the PCI6515 controller, as a master, receives a retry and does not retry the request within 2
15
clock
cycles. The flags are cleared by writing a 1 to the bit. See Table 415 for a complete description of the register
contents.
Bit
7
6
5
4
3
2
1
0
Name
Retry status
Type
RW
RW
RC
R
RC
R
RC
R
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Retry status
90h (Function 0)
Read-only, Read/Write, Read/Clear
C0h
Table 415. Retry Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PCIRETRY
RW
PCI retry time-out counter enable. This bit is encoded as:
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
6
CBRETRY
RW
CardBus retry time-out counter enable. This bit is encoded as:
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
5
TEXP_CBB
RC
CardBus target B retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
4
RSVD
R
Reserved. This bit returns 0 when read.
3
TEXP_CBA
RC
CardBus target A retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
2
RSVD
R
Reserved. This bit returns 0 when read.
1
TEXP_PCI
RC
PCI target retry expired. Write a 1 to clear this bit.
0 = Inactive (default)
1 = Retry has expired.
0
RSVD
R
Reserved. This bit returns 0 when read.
One or more bits in this register are cleared only by the assertion of GRST.
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