Datasheet
5
ISA-to-PC-Card (PCMCIA) Controllers
—
PD6710/
’
22
15.4.3 Preventing Dual Interpretation of DMA Handshake Signals...................99
15.4.4 Turning On DMA System .....................................................................100
15.4.5 The DMA Transfer Process..................................................................100
15.4.6 Terminal Count to Card at Conclusion of Transfer..............................100
Electrical Specifications
......................................................................................101
16.1
Absolute Maximum Ratings...............................................................................101
16.2
DC Specifications..............................................................................................101
16.3
AC Timing Specifications ..................................................................................104
16.4
ISA Bus Timing..................................................................................................104
16.4.1 Reset Timing ........................................................................................107
16.4.2 System Interrupt Timing .......................................................................107
16.4.3 General-Purpose Strobe Timing (PD6722 only)...................................108
16.4.4 Input Clock Specification......................................................................108
16.4.5 PC Card Bus Timing Calculations........................................................109
Package Specifications
.......................................................................................121
17.1
144-Pin LQFP Package.....................................................................................121
17.2
208-Pin MQFP Package....................................................................................122
17.3
208-Pin LQFP Package.....................................................................................123
Order Numbers Example
.....................................................................................124
Appendix A
...............................................................................................................125
19.1
Register Summary Tables.................................................................................125
19.1.1 Operation Registers .............................................................................125
19.2
Chip Control Registers......................................................................................125
19.3
I/O Window Mapping Registers.........................................................................127
19.4
Memory Window Mapping Registers.................................................................129
19.5
Extension Registers ..........................................................................................130
19.6
Timing Registers ..............................................................................................133
16.0
17.0
18.0
19.0
Index
.......................................................................................................................................135