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參數(shù)資料
| 型號(hào)： | PD6710 |
| 廠商： | Intel Corp. |
| 英文描述： | ISA-to-PC-Card (PCMCIA) Controllers |
| 中文描述： | ISA -到- PC卡（PCMCIA）的控制器 |
| 文件頁(yè)數(shù)： | 80/138頁(yè) |
| 文件大?。?/td> | 723K |
| 代理商： | PD6710 |
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PD6710/
’
22
—
ISA-to-PC-Card (PCMCIA) Controllers
80
Datasheet
During a DMA data transfer process, an ISA-based system typically follows its issuance of a DMA
acknowledge with a DMA read or write cycle. However, during a DMA write-verify operation, a
system can issue a DMA acknowledge without following it with a DMA read or write cycle.
Because a DMA-capable PC Card receives DMA acknowledgment only by reception of a DMA
read or write cycle, conditions may occur where the card never receives a DMA acknowledge. To
prevent this from happening in an ISA-based system, a maximum DMA acknowledge delay feature
has been added that generates a
‘
dummy
’
DMA write cycle (reads DMA data from the card) if
there are no system-generated DMA read or write cycles to the card within a programmable time.
Once a DMA acknowledge is received from the system, the PD6722 starts counting the time from
the assertion of the DACK* signal until the system issues a DMA read or write command (IOR* or
IOW*). If this interval exceeds the programmed time, the PD6722 assumes that a system write-
verify is in progress and generates a dummy DMA write cycle at the PC Card interface. This allows
the passing of the DMA acknowledge (and terminal count status) to the card so it can perform any
intended verify-cycle functions.
The maximum DMA acknowledge delay (t2 as shown in
Figure 12
) should be programmed to a
time greater than the maximum time required from the system
’
s issuance of a DMA acknowledge
to its issuance of a DMA read or write cycle (t1 as shown in
Figure 12
). The t1 time is indicated in
the specifications for the systems DMA cycle timing.
Typical system specifications for t1 are 190
–
270 ns, making a value of 80h for the
Maximum
DMA Acknowledge Delay
register suitable for many applications. If the PD6722 is used in an
add-in card application, a value of 20h may be suitable.
Table 14
shows
Maximum DMA
Acknowledge Delay
register values to be programmed for a desired maximum DMA acknowledge
delay.
Figure 12. Selection of Acknowledge Time-out Interval
DREQ
DACK*
AEN
IOR*/IOW*
t2
t1
t1 = time delay from DMA acknowledge to IOR* or IOW* command (specified by system design).
t2 = time to program into the Maximum DMA Acknowledge Delay register for when IOR* or IOW* falling edge does not occur (t2 > t1).
Table 14. Maximum DMA Acknowledge Delay Register Values
(Sheet 1 of 2)
Register Value
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
80h
7 clocks = 280 ns
40h
8 clocks = 320 ns
C0h
9 clocks = 360 ns
20h
10 clocks = 400 ns
A0h
11 clocks = 440 ns
60h
12 clocks = 480 ns
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