參數(shù)資料
型號： PDI1394P24
廠商： NXP Semiconductors N.V.
英文描述： 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口)
中文描述： 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口）
文件頁數(shù)： 10/39頁
文件大?。?/td> 188K
代理商： PDI1394P24
Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
10
9.0
SYMBOL
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITION
MIN
3.0
2.7
1
TYP
3.3
3.0
MAX
3.6
3.6
UNIT
V
V
V
DD
Supply voltage
Source power node
Non-source power node
High-level input voltage, LREQ,
CTL0, CTL1, DO-D7
High-level input voltage, C/LKON
2
,
PC0-PC2, ISO, PD
RESET
Low-level input voltage, LREQ,
CTL0, CTL1, DO-D7
Low-level input voltage, C/LKON
2
,
PC0-PC2, ISO, PD,
RESET
Output current, pins CTLn, Dn,
LNA, C/LKON and SYSCLK
Output current
2.6
5.5
V
V
IH
ISO = V
DD
, V
DD
>= 3.0 V
0.7 V
DD
V
0.6 V
DD
0.7
V
V
IL
ISO = V
DD
0.2 V
DD
V
0.3 V
DD
I
OH
/I
OL
V
OH
= V
DD
–0.5 V, V
OL
= 0.5 V
–12
12
mA
I
O
TPBIAS outputs
TPA, TPB cable inputs, during data reception
TPA, TPB cable inputs, during data arbitration
–6
118
168
1.165
1.165
0.935
0.935
0.523
0.523
2
2.5
260
265
2.515
2.015
1
2.515
2.015
1
2.515
2.015
1
mA
mV
mV
V
V
V
V
V
V
ms
ns
ns
ns
ns
ns
ns
V
ID
Differential input voltage amplitude
Differential in ut voltage am litude
IC 100
V
IC-100
TPB common-mode input voltage
TPB common-mode in ut voltage
Speed signaling
or S100 speed signal
Source power node
Non-source power node
Source power node
Non-source power node
Source power node
Non-source power node
IC 200
V
IC-200
TPB common-mode input voltage
TPB common-mode in ut voltage
S200 speed signal
S200 s eed signal
IC 400
V
IC-400
TPB common-mode input voltage
TPB common-mode in ut voltage
S400 speed signal
S400 s eed signal
t
PU
Power–up reset time
Set by capacitor between RESET pin and GND
TPA, TPB cable inputs, S100 operation
TPA, TPB cable inputs, S200 operation
TPA, TPB cable inputs, S400 operation
Between TPA and TPB cable inputs, S100 operation
Between TPA and TPB cable inputs, S200 operation
Between TPA and TPB cable inputs, S400 operation
Crystal connected according to Figure 9 or external
clock input at pin XI
1.08
0.5
0.315
0.8
0.55
0.5
Receive input jitter
Receive input skew
f
XTAL
Crystal or external clock frequency
24.5735
24.576
24.5785
MHz
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when RESET = 0.
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