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參數(shù)資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數(shù)： | 2/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
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Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2
2000 Jun 23
1.0
Fully supports provisions of IEEE 1394–1995 Standard for high
performance serial bus and the P1394a–2000 Standard.
1
Fully interoperable with Firewire
and i.LINK
implementations of
the IEEE 1394 Standard.
2
Full P1394a support includes:
–
Connection debounce
–
Arbitrated short reset
–
Multispeed concatenation
–
Arbitration acceleration
–
Fly-by concatenation
–
Port disable/suspend/resume
Provides two 1394a fully-compliant cable ports at
100/200/400 Megabits per second (Mbps)
Fully compliant with Open HCI requirements
Cable ports monitor line conditions for active connection to remote
node.
Power down features to conserve energy in battery-powered
applications include:
–
Automatic device power down during suspend
–
Device power down terminal
–
Link interface disable via LPS
–
Inactive ports powered-down
Logic performs system initialization and arbitration functions
Encode and decode functions included for data-strobe bit level
encoding
Incoming data resynchronized to local clock
Single 3.3 volt supply operation
Minimum V
DD
of 2.7 V for end-of-wire power-consuming devices
While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
FEATURES
Supports extended bias-handshake time for enhanced
interoperability with camcorders
Interface to link-layer controller supports low-cost bus-holder
isolation and optional Annex J electrical isolation
Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
Low-cost 24.576 MHz crystal provides transmit, receive data at
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
Does not require external filter capacitors for PLL
Interoperable with link-layer controllers using 3.3 V and 5 V
supplies
Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
Node power class information signaling for system power
management
Cable power presence monitoring
Separate cable bias (TPBIAS) for each port
Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
Function and pin compatible with the Lucent FW802 400 Mbps Phy
2.0
The PDI1394P24 provides the digital and analog transceiver functions
needed to implement a two port node in a cable-based IEEE
1394–1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P24 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21.
DESCRIPTION
3.0
ORDERING INFORMATION
PACKAGE
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
64-pin plastic LQFP
0
°
C to +70
°
C
PDI1394P24 BD
PDI1394P24 BD
SOT314-2
1.
2.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
Firewire is a trademark of Apple Computer Inc. i.LINK is a trademark of Sony.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
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