- 您現(xiàn)在的位置：買賣IC網 > PDF目錄367854 > PDI1394P24 (NXP Semiconductors N.V.) 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) PDF資料下載
參數資料
| 型號： | PDI1394P24 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-port 400 Mbps physical layer interface(2端口 400 Mbps物理層接口) |
| 中文描述： | 2端口400 Mbps的物理層接口（2端口400 Mbps的物理層接口） |
| 文件頁數： | 5/39頁 |
| 文件大?。?/td> | 188K |
| 代理商： | PDI1394P24 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
Philips Semiconductors
Objective specification
PDI1394P24
2-port 400 Mbps physical layer interface
2000 Jun 23
5
Name
Description
I/O
Pin Numbers
Pin Type
DVDD
Supply
7, 17, 26, 27, 62
—
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10
μ
F filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
ISO
CMOS
23
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P24 and LLC, the ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5V tol
16
I
Link Power Status input. This terminal is used to monitor the
active/power status of the link layer controller and to control the state of
the PHY-LLC interface. This terminal should be connected to either the
V
supplying the LLC through a 10 k
resistor, or to a pulsed output
which is active when the LLC is powered. A pulsed signal should be
used when an isolation barrier exists between the LLC and PHY. (See
Figure 8)
The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6
μ
s (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6
μ
s). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.
When the PDI1394P24 detects that LPS is inactive, it will place the
PHY-LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26
μ
s (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.
LREQ
CMOS 5V tol
1
I
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P24. Bus holder is built into this terminal.
NC
No connect
44, 45, 46, 47, 48
—
No connect.
PC0, PC1,
PC2
CMOS 5V tol
20, 21, 22
I
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.
PD
CMOS 5V tol
19
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2
PLLGND
Supply
58
—
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLLVDD
Supply
57
—
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1
μ
F
and 0.001
μ
F. Lower frequency 10
μ
F filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
RESET
CMOS 5V tol
61
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V
is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
相關PDF資料 |
PDF描述 |
|---|---|
| PDI40C1D00 | |
| PDI40C1300 | |
| PDI40C130R | |
| PDI40C130X | |
| PDI40C13R0 | |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PDI1394P24BD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE TRANSCEIVER|CMOS|4 DRIVER|4 RCVR|QFP|64PIN|PLASTIC |
| PDI1394P25 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1-port 400 Mbps physical layer interface |
| PDI1394P25BD | 功能描述:輸入/輸出控制器接口集成電路 1394 1 PORT 400 MB/S PHY RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| PDI1394P25BD,118 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Tape and Reel |
| PDI1394P25BD,151 | 制造商:NXP Semiconductors 功能描述:1394 1 PORT 400 MB/S PHY - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。