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參數(shù)資料
| 型號(hào)： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 266K |
| 代理商： | PE3293 |
PE3293
Product Specification
Functional Description
Copyright
Peregrine Semiconductor Corp. 2003
Page 8 of 18
File No. 70/0015~02C
|
UTSi
CMOS RFIC SOLUTIONS
The Functional Block Diagram in Figure 5 shows a
21-bit serial control register, a multiplexed output,
and PLL sections PLL1 and PLL2. Each PLL
contains a fractional-N main counter chain, a
reference counter, a phase detector, and an internal
charge pump with on-chip fractional spur
compensation. Each fractional-N main counter
chain includes an internal dual modulus prescaler,
supporting counters, and a fractional accumulator.
Serial input data is clocked on the rising edge of
Clock, MSB first. The last two bits are the address
bits that determine the register address. Data is
transferred into the counters as shown in Table 8,
PE3293 Register Set. If the f
o
LD pin is configured
as data out, then the contents of shift register bit S
20
are clocked on the falling edge of Clock onto the
f
o
LD pin. This feature allows the PE3293 and
compatible devices to be connected in a daisy-
chain configuration.
The PLL1 (RF) VCO frequency f
in
1 is related to the
reference frequency f
r
by the following equation:
f
in
1 = [(32 x M
1
) + A
1
+ (F
1
/32)] x (f
r
/R
1
)
(1) Note that A
1
must be less than or equal to M
1
.
Also, f
in
1 must be greater than or equal to 1024 x
(f
r
/R
1
) to obtain contiguous channels.
The PLL2 (IF) VCO frequency f
in
2 is related to the
reference frequency f
r
by the following equation:
f
in
2 = [(16 x M
2
) + A
2
+ (F
2
/32)] x (f
r
/R
2
)
(2) Note that A
2
must be less than or equal to M
2
.
Also, f
in
2 must be greater than or equal to 256 x (f
r
/
R
2
) to obtain contiguous channels.
F
1
sets PLL1 fractionality. If F
1
is an even number,
the PE3293 automatically reduces the fraction. For
example, if F
1
= 12, then the fraction 12/32 is
automatically reduced to 3/8. In this way, fractional
denominators of 2, 4, 8, 16 and 32 are available. F
2
sets the fractionality for PLL2 in the same manner.
Figure 4. Functional Block Diagram
32/33
Prescaler
f
in
1
Fractional Spur
Compensation
Fractional Spur
Compensation
9-bit Reference
Divider
9-bit Reference
Divider
21-bit Serial Control
Interface
Ref.
Amp.
f
r
Clock
Data
LE
f
in
2
16/17
Prescaler
f
o
LD
CP1
CP2
Phase
Detector
Phase
Detector
Charge
Pump
Charge
Pump
Multiplexer
A
Counter
0<A
1
<31
A
Counter
0<A
2
<15
Prescaler
Control Logic
Prescaler
Control Logic
M
Counter
3<M
1
<511
M
Counter
3<M
2
<511
F
Counter
0<F
2
<31
F
Counter
0<F
1
<31
R
2
9
R
1
9
M
2
9
F
2
5
A
2
4
A
1
5
M
1
9
F
1
5
C
22
C
21
C
11
C
12
P
1
P
2
P
1
P
2
C
22
C
22
C
22
C
22
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