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參數(shù)資料
| 型號(hào)： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁(yè)數(shù)： | 11/18頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
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PE3293
Product Specification
Table 11. f
o
LD Programming Truth Table
X = don’t care condition
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2003
Page 11 of 18
f
o
LD
Output State
C
14
(PLL1F
0
)
C
13
(PLL1LD)
C
24
(PLL2F
0
)
C
23
(PLL2LD)
Disabled (Note 1)
0
0
0
0
PLL 1 Lock detect
(Note 2) (LD1)
0
1
0
0
PLL2 Lock detect
(Note 2) (LD2)
0
0
0
1
PLL1 / PLL2 Lock detect
(Note 2)
0
1
0
1
PLL1 Reference divider output (f
c
1)
1
X
0
0
PLL2 Reference divider output (f
c
2)
0
X
1
0
PLL1 Programmable divider output (f
p
1)
1
X
0
1
PLL2 Programmable divider output (f
p
2)
0
X
1
1
Serial data out
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
1
0
Counter reset (Note 3)
1
1
1
1
Note 1:
When the f
o
LD is disabled the output is a CMOS LOW.
Note 2:
Lock detect indicates when the VCO frequency is in “l(fā)ock”. When PLL1 is in lock and PLL1 lock detect is selected, the f
o
LD pin will be HIGH with
narrow pulses LOW. When PLL2 is in lock and PLL2 lock detect is selected, the f
o
LD pin will be HIGH with narrow pulses LOW. When PLL1 / PLL2 lock
detect is selected the f
o
LD pin will be HIGH with narrow pulses LOW only when both PLL1 and PLL2 are in lock.
Note 3:
The counter reset state when activated resets all counters. Upon removal of the reset, counters M, A, and F resume counting in
close alignment with the R counter (the maximum error is one prescaler cycle). The reset bits can be activated to allow smooth
acquisition upon powering up.
Programming the Pre-scaler
P
2
and P
1
are used for internal testing of the prescaler and must be programmed with 0,0 for normal
PLL operation.
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