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參數(shù)資料
| 型號： | PE3293 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 1.8GHz/550MHz Dual Fractional-N Ultra-Low Spurious PLL for Frequency Synthesis |
| 中文描述： | 1.8GHz/550MHz雙分?jǐn)?shù)N超低的雜散鎖相環(huán)頻率合成 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | PE3293 |
PE3293
Product Specification
Table 6. DC Characteristics
Copyright
Peregrine Semiconductor Corp. 2003
Page 6 of 18
File No. 70/0015~02C
|
UTSi
CMOS RFIC SOLUTIONS
V
DD
= 3.0 V, -40
°
C < T
A
< 85
°
C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
I
DD
3 V supply current
C
10
, C
20
= 00 (both PLLs on)
4.0
mA
I
stby
Total standby current
5.0
50
μ
A
Digital inputs: Clock, Data, LE
V
IH
High level input voltage
V
DD
= 2.7 to 3.3 volts
0.7 x V
DD
V
V
IL
Low level input voltage
V
DD
= 2.7 to 3.3 volts
0.3 x V
DD
V
I
IH
High level input current
V
IH
= V
DD
= 3.3 volts
-1
+1
μ
A
I
IL
Low level input current
V
IL
= 0, V
DD
= 3.3 volts
-1
+1
μ
A
Reference Divider input: f
r
I
IHR
Input current
V
IH
= V
DD
= 3.3 volts
+25
μ
A
I
ILR
Input current
V
IL
= 0, V
DD
= 3.3 volts
-25
μ
A
Digital output: f
o
LD
V
OLD
Output voltage LOW
I
out
= 1 mA
0.4
V
V
OHD
Output voltage HIGH
I
out
= -1 mA
V
DD
– 0.4
V
Charge Pump outputs: CP1, CP2
I
CP - Source
-70
μ
A
I
CP - Sink
Drive current
V
CP
= V
DD
/ 2
-70
μ
A
I
CPL
Leakage current
0.5 V < V
CP
< V
DD
– 0.5 volt
-5
5
nA
I
CP – Source
vs.
I
CP - Sink
Sink vs. source mismatch
V
CP
= V
DD
/ 2, T
A
= 25
°
C
10
%
I
CP
vs T
A
Output current vs. temperature
V
CP
= V
DD
/ 2
10
%
I
CP
vs. V
CP
Output current magnitude
variation vs. voltage
0.5 V < V
CP
< V
DD
– 0.5 volt, T
A
= 25
°
C
10
%
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