
PEB 20542
PEF 20542
Register Description (TIMR3)
Data Sheet
5-203
2000-09-14
SRC
Clock Source (valid in clock mode 5 only)
This bit selects the clock source of the internal timer:
SRC =
’
0
’
The timer is clocked by the effective transmit clock.
SRC =
’
1
’
The timer is clocked by the frame-sync synchronization
signal supplied via the FSC pin in clock mode 5.
(all modes)
TMD
Timer Mode
This bit must be set to
’
1
’
if HDLC Automode operation is selected. In all
other protocol modes it must remain
’
0
’
:
TMD=
’
0
’
The timer is controlled by the CPU via access to registers
CMDRL
and
TIMR0
..
TIMR3
.
The timer can be started any time by setting bit
’
STI
’
in
register
CMDRL
. After the timer has expired it generates
a timer interrupt. The timer can be stopped any time by
setting bit
’
TRES
’
in register
CMDRL
to
’
1
’
.
TMD=
’
1
’
The timer is used by the SEROCCO-D for protocol
specific time-out and retry transactions in HDLC
Automode.
(hdlc modes)
CNT(2:0)
Counter
The meaning of this bit field depends on the selected protocol mode.
In HDLC Automode, with bit TMD=
’
1
’
:
Retry Counter (in HDLC protocol known as
’
N2
’
):
Bit field
’
CNT
’
indicates the number of S-Command frames (with poll
bit set) which are transmitted autonomously by SEROCCO-D after
every expiration of the time out period
’
t
’
(determined by
’
TVALUE
’
), in
case an I-Frame gets not acknowledged by the opposite station. The
maximum value is 6 S-command frames. If
’
CNT
’
is set to
’
7
’
, the
number of S-commands is unlimited in case of no acknowledgement.
In all other modes, with bit TMD=
’
0
’
:
Restart Counter :
Bit field
’
CNT
’
indicates the number of automatic restarts which are
performed by SEROCCO-D after every expiration of the time-out
period
’
t
’
, in case the timer is not stopped by setting bit
’
TRES
’
in
register
CMDRL
to
’
1
’
. The maximum value is 6 restarts. If
’
CNT
’
is set
to
’
7
’
, a timer interrupt is generated periodically with time period
’
t
’
determined by bit field
’
TVALUE
’
.
(all modes)