參數(shù)資料
型號： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁數(shù)： 12/50頁
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
12
Datasheet
3.1.3
AGP (60 SIGNALS)
Table 3
lists the Pentium II Processor – Low-Power Module’s AGP interface signals.
Table 3. AGP Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltag
e
Description
GAD[31:0]
I/O
AGP
V_3
AGP Address/Data:
The standard AGP address and data lines. This
bus functions in the same way as the PCI AD[31:0] bus. The address
is driven with FRAME# assertion, and data is driven or received in
following clocks.
GC/BE[3:0]#
I/O
AGP
V_3
AGP Command/Byte Enable:
This bus carries the command
information during AGP cycles when PIPE# is being used. During an
AGP write, this bus contains byte enable information. The command is
driven with FRAME# assertion, and byte enables corresponding to
supplied or requested data are driven on the following clocks.
GFRAME#
I/O
AGP
V_3
AGP Frame:
Not used during AGP transactions. Remains de-
asserted by an internal pullup resistor. Assertion indicates the address
phase of a PCI transfer. Negation indicates that one more data
transfer is desired by the cycle initiator.
GDEVSEL#
I/O
AGP
V_3
AGP Device Select:
Same function as PCI DEVSEL#. Not used
during AGP transactions. This signal is driven by the 443BX Host
Bridge/Controller when a PCI initiator is attempting to access DRAM.
DEVSEL# is asserted at medium decode time.
GIRDY#
I/O
AGP
V_3
AGP Initiator Ready:
Indicates the AGP compliant target is ready to
provide ALL write data for the current transaction. Asserted when the
initiator is ready for a data transfer.
GTRDY#
I/O
AGP
V_3
AGP Target Ready:
Indicates the AGP compliant master is ready to
provide ALL write data for the current transaction. Asserted when the
target is ready for a data transfer.
GSTOP#
I/O
AGP
V_3
AGP Stop:
Same function as PCI STOP#. Not used during AGP
transactions. Asserted by the target to request the master to stop the
current transaction.
GREQ#
I
AGP
V_3
AGP Request:
AGP master requests for AGP.
GGNT#
O
AGP
V_3
AGP Grant:
Same function as on PCI. Additional information is
provided on the ST[2:0] bus. PCI Grant: Permission is given to the
master to use PCI.
GPAR
I/O
AGP
V_3
AGP Parity:
A single parity bit is provided over GAD[31:0] and
GC/BE[3:0]. This signal is not used during AGP transactions.
PIPE#
I
AGP
V_3
Pipelined Request:
Asserted by the current master to indicate a full
width address is to be queued by the target. The master queues one
request each rising clock edge while PIPE# is asserted.
SBA[7:0]
I
AGP
V_3
Sideband Address:
This bus provides an additional conduit to pass
address and commands to the 443BX Host Bridge/Controller from the
AGP master.
RBF#
I
AGP
V_3
Read Buffer Full:
Indicates if the master is ready to accept previously
requested low priority read data.
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