參數(shù)資料
型號(hào)： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁(yè)數(shù)： 40/50頁(yè)
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
40
Datasheet
4.8.4
Stop Grant State
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop
requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the
Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the
Normal state can be made by the de-assertion of the STPCLK# signal, or the occurrence of a stop
break event (a BINIT#, FLUSH# or RESET# assertion).
While in the Stop Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the normal state. Only one occurrence of each event
will be recognized upon return to the normal state.
The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization
unless STPCLK# has been deasserted.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Stop Grant state after initialization until STPCLK# is deasserted.
If the FLUSH# signal is asserted, the processor will flush the on-chip and off-chip caches and
return to the Stop Grant state. A transition to the Sleep state can be made by the assertion of the
SLP# signal.
4.8.4.1
Quick Start State
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the system bus priority
device. Because of its snooping behavior, Quick Start can only be used in a Uniprocessor (UP)
configuration.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal
is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupt, servicing snoop transactions from symmetric bus masters or responding to
FLUSH# or BINIT# assertions. While the processor is in the Quick Start state, it will not respond
properly to any input signal other than STPCLK#, RESET# or BPRI#. If any other input signal
changes, then the behavior of the processor will be unpredictable. No serial interrupt messages may
begin or be in progress while the processor is in the Quick Start state. The thermal sensor will
respond normally to SMBus transactions when the processor is in the Quick Start state.
RESET# assertion will cause the processor to immediately initialize itself, but the processor will
stay in the Quick Start state after initialization until STPCLK# is deasserted.
Asserting the SLP# signal when the processor is configured for Quick Start will result in
unpredictable behavior and is not recommended.
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