參數(shù)資料
型號： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁數(shù)： 27/50頁
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
27
4.4.2
AC Requirements
Please refer to Table 16 for module AC timing requirements for BCLK.
BCLK system timing is specified in terms of signal quality. The waveform of Figure 6 describes a
typical system bus clock as seen at the processor core pin.
Table 16. Module AC Specifications (BCLK) at the Processor Core Pins
T#
Parameter
Min
Nom
Max
Unit
Figure
Notes
1,2,3
System Bus Frequency
66.67
MHz
All processor core
frequencies
T1:
BCLK Period
15.
ns
4, 5, 6
T2:
BCLK Period Stability
±250
ps
6, 7, 8, 9
T3:
BCLK High Time
5.3
ns
@>1.765 V
6
T4:
BCLK Low Time
5.3
ns
@<0.5 V
6
T5:
BCLK Rise Time
0.175
0.875
ns
(0.9 V-1.6 V)
6,9
T6:
BCLK Fall Time
0.175
0.875
ns
(1.6 V–0.9 V)
6,9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all modules.
2. All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All GTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the system bus clock. The system bus clock to core clock
ratio is determined during initialization as described and is predetermined by the module.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the
CK97 Clock
Synthesizer/Driver Specification
for further information.
6. This specification applies to the Pentium
II
processor system bus frequency of 66 MHz.
7. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
8. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than
500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the
CKDM66-M Clock Synthesizer/Driver Specification
for further details.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
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