參數(shù)資料
型號(hào)： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁(yè)數(shù)： 28/50頁(yè)
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
28
Datasheet
4.4.2.1
System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines
Table 17 describes the signal quality specifications at the processor core for the module system bus
clock (BCLK) signal. Figure 3 describes the signal quality waveform for the system bus clock at
the processor core pins.
Table 17. BCLK Signal Quality Specifications for Simulation at the Processor Core
T#
Parameter
Min
Nom
Max
Unit
Figure
Notes
1
V1:
BCLK V
IL
0.5
V
3
V2:
BCLK V
IH
1.765
V
3
2
V3:
V
IN
Absolute Voltage Range
–0.8
3.3
V
3
2
V4:
Rising Edge Ringback
1.765
V
3
3, 4
V5:
Falling Edge Ringback
0.5
V
3
4
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all modules.
2. This is the Pentium
II
processor system bus clock overshoot and undershoot specification for 66-MHz
system bus operation.
3. Clock signal must be monotonic from +0.5 V to +1.765 V.
4. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
specification is an absolute value.
Figure 3. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
V2
V1
V3
V3
T3
V5
V4
T6
T4
T5
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