參數(shù)資料
型號： Pentium III cpu with mobile
廠商： Intel Corp.
英文描述： Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器)
中文描述： 奔騰III處理器的移動模塊連接器2（絲裂霉素2）（帶移動模塊連接器2奔三處理器）
文件頁數(shù)： 27/64頁
文件大小： 773K
代理商： PENTIUM III CPU WITH MOBILE
Pentium
III Processor Mobile Module MMC-2
245304-003
Datasheet
21
Extended Data Out (EDO) DRAM
66-MHz memory bus
The clocking architecture supports the use of SDRAM. The clocking mode for 100-MHz SDRAM
memory configurations allows all host and SDRAM clocks to be generated from the same clocking
source on the system electronics. For complete details about memory device support, organization,
size, and addressing when using SDRAM memory and trace length guidelines, refer to the
Intel
Pentium
III
Processor Mobile Module System Electronics 100-MHz Layout Guidelines Revision.
1.0
(OR-1780).
4.3.2
Reset Strap Options
Several strap options on the memory address bus define the behavior of the Pentium
III
processor
mobile module after reset. Other straps are allowed to override the default settings.
Table 13
shows
the various straps and their implementation.
4.3.3
PCI Interface
The PCI interface of the 82443BX Host Bridge is available at the MMC-2 connector. The
82443BX Host Bridge supports the PCI Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain signal when they require the use of the PCI
interface. Refer to the
PCI Mobile Design Guide
for complete details on the PCI Clockrun
protocol.
The 82443BX Host Bridge is responsible for arbitrating the PCI bus. The 82443BX Host Bridge
can support up to five PCI bus masters. There are five PCI Request/Grant pairs (REQ[4:0]# and
GNT[4:0]#) available on the connector to the system electronics.
Note:
The PCI interface on the MMC-2 connector is 3.3V only. PCI devices that are 5.0V are not
supported.
The 82443BX Host Bridge system controller is compliant with the
PCI 2.1 Specification
, which
improves the worst case PCI bus access latency from earlier PCI specifications. The 82443BX
Host Bridge supports only Mechanism #1 for accessing PCI configuration space. This implies that
signals AD[31:11] are available for PCI IDSEL signals. However, since the 82443BX Host Bridge
Table 13. Configuration Straps for the 82443BX Host Bridge System Controller
Signal
Function
Module Default Setting
Optional Override on
System Electronics
MAB[12]#
Host Frequency Select
Strapped high on the module for 100
MHz
None
MAB[11]#
In Order Queue Depth
No strap, maximum queue depth is set
at 8
None
MAB[10]#
Quick Start Select
Strapped high on the module for Quick
Start mode
None
MAB[9]#
AGP Disable
No strap (AGP is enabled)
Strap high to disable AGP
MAB[7]#
MM Configuration
No strap (standard MMC-2 mode)
None
MAB[6]#
Host Bus Buffer Mode
Select
Strapped high on the module for
mobile PSB buffers
None
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