參數(shù)資料
型號： pentium processor with MMX
廠商： Intel Corp.
英文描述： 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述： 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器）
文件頁數(shù)： 16/51頁
文件大小： 479K
代理商： PENTIUM PROCESSOR WITH MMX
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
16
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of a
bus cycle. If this pin is sampled active, the Pentium processor with MMX
technology will latch the address and control signals in the machine check
registers. If, in addition, the MCE bit in CR4 is set, the Pentium processor with
MMX technology will vector to the machine check exception.
NOTE:
To assure that BUSCHK# will always be recognized, STPCLK# must be
deasserted any time BUSCHK# is asserted by the system, before the system
allows another external bus cycle. If BUSCHK# is asserted by the system for a
snoop cycle while STPCLK# remains asserted, usually (if MCE=1) the processor
will vector to the exception after STPCLK# is deasserted. But if another snoop to
the same line occurs during STPCLK# assertion, the processor can lose the
BUSCHK# request.
CACHE#
O
For Pentium processor with MMX technology-initiated cycles the
cache
pin
indicates internal cacheability of the cycle (if a read), and indicates a burst write
back cycle (if a write). If this pin is driven inactive during a read cycle, the Pentium
processor with MMX technology will not cache the returned data, regardless of the
state of the KEN# pin. This pin is also used to determine the cycle length (number
of transfers in the cycle).
CLK
I
The
clock
input provides the fundamental timing for the Pentium processor with
MMX technology. Its frequency is the operating frequency of the Pentium
processor with MMX technology external bus, and requires TTL levels. All
external timing parameters except TDI, TDO, TMS, TRST#, and PICD0-1 are
specified with respect to the rising edge of CLK.
This pin is 3.3V-tolerant-only on the Pentium processor with MMX technology.
Please refer to the Pentium
Processor Family Developer’s Manual
(Order
Number 241428) for the CLK and PICCLK signal quality specification.
NOTE:
It is recommended that CLK begin toggling within 150 ms after V
CC
reaches its
proper operating level. This recommendation is to ensure long-term reliability of
the device.
CPUTYP
I
CPU type
distinguishes the Primary processor from the Dual processor. In a
single processor environment, or when the Pentium processor with MMX
technology is acting as the Primary processor in a dual processing system,
CPUTYP should be strapped to V
SS
. The Dual processor should have CPUTYP
strapped to V
CC3
.
D/C#
O
The
data/code
output is one of the primary bus cycle definition pins. It is driven
valid in the same clock as the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.
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