參數(shù)資料
型號: pentium processor with MMX
廠商: Intel Corp.
英文描述: 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述: 32位MMX技術(shù)(32位帶MMX公司的技術(shù)處理器處理器)
文件頁數(shù): 24/51頁
文件大?。?/td> 479K
代理商: PENTIUM PROCESSOR WITH MMX
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
E
24
5/23/97 10:47 AM 24318502.DOC
2.4.
Pin Reference Tables
Table 4. Output Pins
Name
Active Level
When Floated
ADS#
(1)
Low
Bus Hold, BOFF#
ADSC#
Low
Bus Hold, BOFF#
APCHK#
Low
BE7#-BE4#
Low
Bus Hold, BOFF#
BREQ
High
CACHE#
(1)
Low
Bus Hold, BOFF#
D/P#
(2)
N/A
FERR#
(2)
Low
HIT#
(1)
Low
HITM#
(1, 3)
Low
HLDA
(1)
High
IERR#
Low
LOCK#
(1)
Low
Bus Hold, BOFF#
M/IO#
(1)
, D/C#
(1)
, W/R#
(1)
N/A
Bus Hold, BOFF#
PCHK#
Low
BP3-2, PM1/BP1, PM0/BP0
High
PRDY
High
PWT, PCD
High
Bus Hold, BOFF#
SCYC
(1)
High
Bus Hold, BOFF#
SMIACT#
Low
TDO
N/A
All states except Shift-DR and Shift-IR
V
CC
2DET#
Low
NOTES:
All output and input/output pins are floated during tristate test mode (except IERR#).
1.
These are I/O signals when two Pentium
processor with MMX technology are operating in dual processing mode.
2.
These signals are undefined when the processor is configured as a Dual processor.
3.
M# pin has an internal pull-up resistor.
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