參數(shù)資料
型號(hào)： pentium processor with MMX
廠商： Intel Corp.
英文描述： 32-bit processor with MMX technology(32位帶MMX技術(shù)處理器)
中文描述： 32位MMX技術(shù)（32位帶MMX公司的技術(shù)處理器處理器）
文件頁(yè)數(shù)： 19/51頁(yè)
文件大小： 479K
代理商： PENTIUM PROCESSOR WITH MMX
E
PENTIUM PROCESSOR WITH MMX TECHNOLOGY
19
5/23/97 10:47 AM 24318502.DOC
Table 2. Quick Pin Reference
(Cont’d)
Symbol
Type
Name and Function
IERR#
O
The
internal error
pin is used to indicate internal parity errors. If a parity error
occurs on a read from an internal array, the Pentium processor with MMX
technology will assert the IERR# pin for one clock and then shutdown.
IGNNE#
I
This is the
ignore numeric error
input. This pin has no effect when the NE bit in CR0 is
set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the Pentium
processor with MMX technology will ignore any pending unmasked numeric exception
and continue executing floating-point instructions for the entire duration that this pin is
asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked
numeric exception exists (SW.ES = 1), and the floating-point instruction is one of FINIT,
FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM, the Pentium
processor with MMX technology will execute the instruction in spite of the pending
exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending unmasked
numeric exception exists (SW.ES = 1), and the floating-point instruction is one other
than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM,
the Pentium processor with MMX technology will stop execution and wait for an external
interrupt.
IGNNE# is internally masked when the Pentium processor with MMX technology is
configured as a Dual processor.
INIT
I
The Pentium processor with MMX technology
initialization
input pin forces the
Pentium processor with MMX technology to begin execution in a known state. The
processor state after INIT is the same as the state after RESET except that the
internal caches, write buffers, and floating-point registers retain the values they had
prior to INIT. INIT may NOT be used in lieu of RESET after power-up.
If INIT is sampled high when RESET transitions from high to low, thePentium
processor with MMX technology will perform built-in self test prior to the start of
program execution.
INTR/LINT0
I
An active
maskable interrupt
input indicates that an external interrupt has been
generated. If the IF bit in the EFLAGS register is set, thePentium processor with
MMX technology will generate two locked interrupt acknowledge bus cycles and
vector to an interrupt handler after the current instruction execution is completed.
INTR must remain active until the first interrupt acknowledge cycle is generated to
assure that the interrupt is recognized.
If the local APIC is enabled, this pin becomes LINT0.
INV
I
The
invalidation
input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in the
clock EADS# is sampled active.
KEN#
I
The
cache enable
pin is used to determine whether the current cycle is
cacheable or not and is consequently used to determine cycle length. When the
Pentium processor with MMX technology generates a cycle that can be cached
(CACHE# asserted) and KEN# is active, the cycle will be transformed into a burst
line fill cycle.
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