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參數(shù)資料
| 型號(hào)： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 12/35頁 |
| 文件大小： | 550K |
| 代理商： | PENTIUM PROCESSOR |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
E
12
9/19/97 1:03 PM SPEIDEN_.DOC
2.1.5.
CLOCK (8 SIGNALS)
Table 6 lists the
Intel Mobile Module’s clock signals.
Table 6. Clock Signal Descriptions
Name
Direction
Voltage
Description
*OEM_PD
I
V_3
OEM Pull-Down:
A pull-down resistor of 1K ohms is required on
OEM_PD.
PCLK
I
V_3S
PCI Clock In:
PCLK is an input to the module from the CKDM66-M
clock source and is one of the system’s PCI clocks.
This clock is
used by all of the 430TX PCIset logic in the PCI clock domain.
This
clock is stopped when the PIIX4 ISA bridge PCI_STP# signal is
asserted.
HCLK[1:0]
I
V_CPUIO
Host Clock In:
These pins are used solely for CKDM66-M Host clocking.
This
clock is used by the processor, 430TX PCIset and L2.
This clock is stopped
when the PIIX4 ISA bridge PCI_STP# signal is asserted.
Suspend Clock:
32 KHz input for DRAM refresh circuitry and
clocking events in suspend state.
The DRAM refresh during suspend
and non-suspend states is performed based on this clock.
SUSCLK
I
V_3
FQS[1:0]
0
V_3S
Frequency Status:
Provides status of the host clock frequency to the
I/O Module.
These signals are static and are pulled either low or high
to the V_3S voltage.
FQS1
0
0
1
1
FQS0
0
1
0
1
Frequency
60 MHz
66 MHz
Reserved
Reserved
CPU3.3_2.5#
O
V_CPUIO
Clock Voltage Select:
Provides status to the I/O module about the
voltage level at which the CKDM66-M clock generator should be
operating.
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