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| 型號： | pentium processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Processor With MMX And Mobile Module(32位帶移動(dòng)模塊和MMX技術(shù)CPU) |
| 中文描述： | 32位處理器MMX和移動(dòng)模塊（32位帶移動(dòng)模塊和MMX公司技術(shù)的CPU） |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 550K |
| 代理商： | PENTIUM PROCESSOR |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
E
2.1.2.
PCI (56 SIGNALS)
8
9/19/97 1:03 PM SPEIDEN_.DOC
Table 3 lists the
Intel Mobile Module’s PCI interface signals.
Table 3. PCI Signal Descriptions
Name
Type
Voltage
Description
AD[31:0]
I/O
V_3S
Address/Data:
The standard PCI address and data lines. The address is
driven with FRAME# assertion, and data is driven or received in following
clocks.
C/BE[3:0]#
I/O
V_3S
Command/Byte Enable:
The command is driven with FRAME#
assertion, and byte enables corresponding to supplied or requested data
are driven on following clocks.
FRAME#
I/O
V_3S
Frame:
Assertion indicates the address phase of a PCI transfer.
Negation indicates that one more data transfer is desired by the cycle
initiator.
DEVSEL#
I/O
V_3S
Device Select:
This signal is driven by the 430TX PCIset when a PCI
initiator is attempting to access DRAM.
DEVSEL# is asserted at medium
decode time.
IRDY#
I/O
V_3S
Initiator Ready:
Asserted when the initiator is ready for data transfer.
TRDY#
I/O
V_3S
Target Ready:
Asserted when the target is ready for a data transfer.
STOP#
I/O
V_3S
Stop:
Asserted by the target to request the master to stop the current
transaction.
LOCK#
I/O
V_3S
Lock:
Used to establish, maintain and release resource locks on PCI.
REQ[3:0]#
I
V_3S
PCI Request:
PCI master requests for PCI.
GNT[3:0]#
O
V_3S
PCI Grant:
Permission is given to the master to use PCI.
*PHOLD#
I
V_3S
PCI Hold:
This signal comes from the expansion bridge; it is the bridge
request for PCI.
The 430TX PCIset will drain the DRAM write buffers,
drain the processor-to-PCI posting buffers, and acquire the host bus
before granting the request via PHLDA#. This ensures that GAT timing is
met for ISA masters.
The PHOLD# protocol has been modified to include
support for passive release.
*PHLDA#
O
V_3S
PCI Hold Acknowledge:
This signal is driven by the 430TX PCIset to
grant PCI to the expansion bridge.
The PHLDA# protocol has been
modified to include support for passive release.
PAR
I/O
V_3S
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]
SERR#
(RESERVED)
O
V_3S
System Error:
This signal is not implemented in the 430TX PCIset and is
reserved for future modules.
*CLKRUN#
I/O
V_3S
Clock Run:
An open-drain output and also an input.
The 430TX PCIset
requests the central resource (PIIX4 ISA bridge) to start or maintain the
PCI clock by asserting CLKRUN#.
The 430TX PCIset tri-states
CLKRUN# upon deassertion of Reset (since CLK is running upon
deassertion of Reset). An external 2.7K pullup resistor is required.
PCI_RST#
I
V_3S
Reset:
When asserted, this signal asynchronously resets the 430TX
PCIset.
The PCI signals also tri-state, compliant with PCI Rev 2.0 and 2.1
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