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參數(shù)資料
| 型號(hào)： | PH28F640L18T85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, LEAD FREE, VFBGA-56 |
| 文件頁數(shù)： | 59/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | PH28F640L18T85 |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
59
Before issuing a new command, the Status Register contents should be examined and then cleared
using the Clear Status Register command. Any valid command can follow, when word
programming has completed.
11.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and
programming algorithms. However, factory word programming enhances the programming
performance with V
PP
= V
PPH
. This can enable faster programming times during OEM
manufacturing processes. Factory word programming is not intended for extended use. See
Section
5.2, “Operating Conditions” on page 25
for limitations when V
PP
= V
PPH
.
Note:
When V
PP
= V
PPL
, the device draws programming current from the V
CC
supply. If V
PP
is driven
by a logic signal, V
PPL
must remain above V
PPL
MIN to program the device. When V
PP
= V
PPH
,
the device draws programming current from the V
PP
supply.
Figure 27, “Example VPP Supply
Connections” on page 63
shows examples of device power supply configurations.
11.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For Buffered
Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed
into the flash memory array in buffer-size increments. This can improve system programming
performance significantly over non-buffered programming.
When the Buffered Programming Setup command is issued (see
Section 9.2, “Device Commands”
on page 47
), Status Register information is updated and reflects the availability of the write buffer.
SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not
available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7].
When SR[7] is set, the buffer is ready for loading. (see
Figure 41, “Buffer Program Flowchart” on
page 87
).
On the next write, a word count is written to the device at the buffer address. This tells the device
how many data words will be written to the buffer, up to the maximum size of the buffer.
On the next write, a device start address is given along with the first data to be written to the flash
memory array. Subsequent writes provide additional device addresses and data. All data addresses
must lie within the start address plus the word count. Optimum programming performance and
lower power usage are obtained by aligning the starting address at the beginning of a 32-word
boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total
programming time.
After the last data is written to the buffer, the Buffered Programming Confirm command must be
issued to the original block address. The WSM begins to program buffer contents to the flash
memory array. If a command other than the Buffered Programming Confirm command is written to
the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error
occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4]
are set, indicating a programming failure.
Reading from another partition is allowed while data is being programmed into the array from the
write buffer (see
Section 14.0, “Dual-Operation Considerations” on page 71
).
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