- 您現在的位置：買賣IC網 > PDF目錄367934 > PH28F640L18T85 (INTEL CORP) StrataFlash Wireless Memory PDF資料下載
參數資料
| 型號： | PH28F640L18T85 |
| 廠商： | INTEL CORP |
| 元件分類： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA56 |
| 封裝： | 0.75 MM PITCH, LEAD FREE, VFBGA-56 |
| 文件頁數： | 75/106頁 |
| 文件大小： | 1272K |
| 代理商： | PH28F640L18T85 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當前第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
75
15.0
Special Read States
The following sections describe non-array read states. Non-array reads can be performed in
asynchronous read or synchronous burst mode. A non-array read operation occurs as asynchronous
single-word mode. When non-array reads are performed in asynchronous page mode only the first
data is valid and all subsequent data are undefined. When a non-array read operation occurs as
synchronous burst mode, the same word of data requested will be output on successive clock edges
until the burst length requirements are satisfied.
Each partition can be in one of its read states independent of other partitions’ modes. See
Figure 11,
“Asynchronous Single-Word Read with ADV# Low” on page 33
and
Figure 14, “Synchronous
Single-Word Array or Non-array Read Timing” on page 35
for details.
15.1
Read Status Register
The status of any partition is determined by reading the Status Register from the address of that
particular partition. To read the Status Register, issue the Read Status Register command within the
desired partition’s address range. Status Register information is available at the partition address to
which the Read Status Register, Word Program, or Block Erase command was issued. Status
Register data is automatically made available following a Word Program, Block Erase, or Block
Lock command sequence. Reads from a partition after any of these command sequences outputs
that partition’s status until another valid command is written to that partition (e.g. Read Array
command).
The Status Register is read using single asynchronous-mode or synchronous burst mode reads.
Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In asynchronous
mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status
Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV#
must be toggled to update status data. The Status Register read operations do not affect the read
state of the other partitions.
The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit
(SR[0]) indicates whether the addressed partition or some other partition is actively programming
or erasing. Status register bits SR[6:1] present status and error information about the program,
erase, suspend, V
PP
, and block-locked operations.
Table 16.
Status Register Description (Sheet 1 of 2)
Status Register (SR)
Default Value = 0x80
Device
Write Status
Erase
Suspend
Status
Erase
Status
Program
Status
V
PP
Status
Program
Suspend
Status
Block-
Locked
Status
Partition
Status
DWS
ESS
ES
PS
VPPS
PSS
BLS
PWS
7
6
5
4
3
2
1
0
Bit
Name
Description
7
Device Write Status
(DWS)
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
6
Erase Suspend Status
(ESS)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
相關PDF資料 |
PDF描述 |
|---|---|
| PH2907A | PNP switching transistor |
| PH2907 | PNP switching transistor |
| PH2931-135S | Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SO; No of Pins: 16; Temperature Range: -40°C to +85°C |
| PH2931-I3 | Radar Pulsed Power Transistor, 135W, 20ms Pulse, 1% Duty 2.9 - 3.1 GHz |
| PH2931-20M | Radar Pulsed Power Transistor, 20W,100ms Pulse, 10% Duty 2.9-3.1 GHz |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PH28F640W18BD60 | 制造商:Micron Technology Inc 功能描述:PH28F640W18BD60S L785 |
| PH28F640W18BD60B | 制造商:Micron Technology Inc 功能描述:NUMPH28F640W18BD60B PH28F640W18BD60S L78 |
| PH28F640W18TE60B | 制造商:Micron Technology Inc 功能描述:64MB, CRYSTAL .75 VFBGA 1.8 LF - Tape and Reel |
| PH28F640W30BD70A | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel/Serial 1.8V 64Mbit 4M x 16bit 70ns 56-Pin VFBGA Tray 制造商:Micron Technology Inc 功能描述:NUMPH28F640W30BD70A MM#862859FLASH 28F64 |
| PH2-8-SGA | 制造商:Adam Technologies Inc 功能描述:PH2 Series Dual Row 8 Position Straight 2.54 mm Centerline Pin Header |
發(fā)布緊急采購，3分鐘左右您將得到回復。