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參數(shù)資料
| 型號： | PHP55N04LT |
| 英文描述： | TRANSISTOR | MOSFET | N-CHANNEL | 35V V(BR)DSS | 55A I(D) | TO-220AB |
| 中文描述： | 晶體管| MOSFET的| N溝道| 35V的五（巴西）直| 55A條（?。﹟ TO - 220AB現(xiàn)有 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 117K |
| 代理商： | PHP55N04LT |
Philips Semiconductors
Product specification
N-channel TrenchMOS
transistor
Logic level FET
PHP55N04LT, PHB55N04LT
PHD55N04LT
FEATURES
SYMBOL
QUICK REFERENCE DATA
V
DSS
= 35 V
’Trench’
technology
Very low on-state resistance
Fast switching
Low thermal resistance
Logic level compatible
I
D
= 55 A
R
DS(ON)
≤
14 m
(V
GS
= 10 V)
R
DS(ON)
≤
18 m
(V
GS
= 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’
trench
’ technology.
Applications:-
High frequency computer motherboard d.c. to d.c. converters
High current switching
The PHP55N04LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N04LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD55N04LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB)
SOT404 (D
2
PAK)
SOT428 (DPAK)
PIN
DESCRIPTION
1
gate
2
drain
1
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
Drain-source voltage
V
DGR
Drain-gate voltage
V
GS
Gate-source voltage (DC)
V
GSM
Gate-source voltage (pulse
peak value)
I
D
Drain current (DC)
CONDITIONS
T
j
= 25 C to 175C
T
j
= 25 C to 175C; R
GS
= 20 k
MIN.
-
-
-
-
MAX.
35
35
±
15
±
20
UNIT
V
V
V
V
T
j
≤
150C
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
-
-
-
55
38
220
A
A
A
I
DM
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
P
tot
T
j
, T
stg
T
mb
= 25 C
-
103
175
W
C
- 55
d
g
s
1 2 3
tab
1
3
tab
2
1
2
3
tab
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
January 2001
1
Rev 1.000
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