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參數(shù)資料
型號(hào)： PIC16F1527T-I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 28/94頁(yè)
文件大?。?/td> 0K
描述： MCU 28KB FLASH 1536B RAM 64-TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® XLP™ 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲(chǔ)器容量： 28KB（16K x 14）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 30x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 帶卷 (TR)
196
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
20. USART in SPI Mode
20.1
Features
Full Duplex, Three-wire Synchronous Data Transfer
Master Operation
Supports all four SPI Modes of Operation (Mode 0, 1, 2, and 3)
LSB First or MSB First Data Transfer (Configurable Data Order)
Queued Operation (Double Buffered)
High Resolution Baud Rate Generator
High Speed Operation (fXCKmax = f
CK/2)
Flexible Interrupt Generation
20.2
Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be
set to a master SPI compliant mode of operation.
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of opera-
tion the SPI master control logic takes direct control over the USART resources. These
resources include the transmitter and receiver shift register and buffers, and the baud rate gen-
erator. The parity generator and checker, the data and clock recovery logic, and the RX and TX
control logic is disabled. The USART RX and TX control logic is replaced by a common SPI
transfer control logic. However, the pin control logic and interrupt generation logic is identical in
both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the
control registers changes when using MSPIM.
20.3
Clock Generation
The Clock Generation logic generates the base clock for the Transmitter and Receiver. For
USART MSPIM mode of operation only internal clock generation (i.e. master operation) is sup-
ported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one
(i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous mas-
ter mode. The baud rate or UBRRn setting can therefore be calculated using the same
equations, see Table 20-1:
Table 20-1.
Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud
Rate(1)
Equation for Calculating UBRRn
Value
Synchronous Master
mode
BAUD
fOSC
2
UBRRn 1
+
()
---------------------------------------
=
UBRRn
fOSC
2
BAUD
--------------------
1
–
=
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