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PIC16(L)F1526/27
DS41458A-page 30
Preliminary
2011 Microchip Technology Inc.
TABLE 3-2:
SPECIAL FUNCTION REGISTER SUMMARY
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch PORTA
PORTA Data Latch when written: PORTA pins when read
xxxx xxxx uuuu uuuu
00Dh PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
00Eh PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
00Fh PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
010h PORTE
PORTE Data Latch when written: PORTE pins when read
xxxx xxxx uuuu uuuu
011h PIR1
TMR1GIF
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
012h PIR2
OSFIF
TMR5GIF TMR3GIF
—
BCL1IF
TMR10IF
TMR8IF
CCP2IF
000- 0000 000- 0000
013h PIR3
CCP6IF
CCP5IF
CCP4IF
CCP3IF
TMR6IF
TMR5IF
TMR4IF
TMR3IF
0000 0000 0000 0000
014h PIR4
CCP10IF
CCP9IF
RC2IF
TX2IF
CCP8IF
CCP7IF
BCL2IF
SSP2IF
0000 0000 0000 0000
015h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
016h TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
017h TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
018h T1CON
TMR1CS<1:0>
T1CKPS<1:0>
SOSCEN
T1SYNC
—TMR1ON 0000 00-0 uuuu uu-u
019h T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
0000 0x00 uuuu uxuu
01Ah TMR2
Timer 2 Module Register
0000 0000 0000 0000
01Bh PR2
Timer 2 Period Register
1111 1111 1111 1111
01Ch T2CON
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
01Dh —
Unimplemented
—
01Eh —
Unimplemented
—
01Fh —
Unimplemented
—
Bank 1
08Ch TRISA
PORTA Data Direction Register
1111 1111 1111 1111
08Dh TRISB
PORTB Data Direction Register
1111 1111 1111 1111
08Eh TRISC
PORTC Data Direction Register
1111 1111 1111 1111
08Fh TRISD
PORTD Data Direction Register
1111 1111 1111 1111
090h TRISE
PORTE Data Direction Register
1111 1111 1111 1111
091h PIE1
TMR1GIE
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
092h PIE2
OSFIE
TMR5GIE TMR3GIE
—
BCL1IE
TMR10IE
TMR8IE
CCP2IE
000- 0000 000- 0000
093h PIE3
CCP6IE
CCP5IE
CCP4IE
CCP3IE
TMR6IE
TMR5IE
TMR4IE
TMR3IE
0000 0000 0000 0000
094h PIE4
CCP10IE
CCP9IE
RC2IE
TX2IE
CCP8IE
CCP7IE
BCL2IE
SSP2IE
0000 0000 0000 0000
095h OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS<2:0>
1111 1111 1111 1111
096h PCON
STKOVF
STKUNF
—RWDT
RMCLR
RI
POR
BOR
00-1 11qq qq-q qquu
097h WDTCON
—
—WDTPS<4:0>
SWDTEN --01 0110 --01 0110
098h —
Unimplemented
—
099h OSCCON
—
IRCF<3:0>
—SCS<1:0>
-011 1-00 -011 1-00
09Ah OSCSTAT
SOSCR
—
OSTS
HFIOFR
—
LFIOFR
HFIOFS
0-q0 --00 q-qq --0q
09Bh ADRESL
A/D Result Register Low
xxxx xxxx uuuu uuuu
09Ch ADRESH
A/D Result Register High
xxxx xxxx uuuu uuuu
09Dh ADCON0
—
CHS<4:0>
GO/DONE
ADON
-000 0000 -000 0000
09Eh ADCON1
ADFM
ADCS<2:0>
—
ADPREF<1:0>
0000 --00 0000 --00
09Fh —
Unimplemented
—
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
PIC16F1526/7 only.
2:
Unimplemented, read as ‘1’.