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參數(shù)資料
| 型號： | PIC16F688-I/SL |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 8/204頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 4KX14 14SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 57 |
| 系列： | PIC® 16F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 639 (CN2011-ZH PDF) |
| 配用： | XLT14SO-1-ND - SOCKET TRANSITION 14SOIC 150/208 AC162061-ND - HEADER INTRFC MPLAB ICD2 20PIN AC162056-ND - HEADER INTERFACE ICD2 16F688 |
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2009 Microchip Technology Inc.
DS41203E-page 103
PIC16F688
10.4
EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
10.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for Synchronous Master operation:
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
10.4.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device
configured as a master transmits the clock on the TX/
CK line. The TX/CK pin is automatically configured as
an output when the EUSART is configured for
synchronous transmit operation. Serial data bits
change on the leading edge to ensure they are valid at
the trailing edge of each clock. One clock cycle is
generated for each data bit. Only as many clock cycles
are generated as there are data bits.
10.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCTL register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
10.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character, the new character data is held in
the TXREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
10.4.1.4
Synchronous Master Transmission
Set-up:
1.
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 10.3 “EUSART
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3.
Disable Receive mode by clearing bits SREN
and CREN.
4.
Enable Transmit mode by setting the TXEN bit.
5.
If 9-bit transmission is desired, set the TX9 bit.
6.
If interrupts are desired, set the TXIE, GIE and
PEIE interrupt enable bits.
7.
If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8.
Start transmission by loading data to the
TXREG register.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16F688IST | 制造商:MICROCHIP 功能描述:New |
| PIC16F688T-E/SL | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F688T-E/ST | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16F688T-E/ST VAO | 制造商:Microchip Technology Inc 功能描述: |
| PIC16F688T-I/ML | 功能描述:8位微控制器 -MCU 7KB 256 RAM 12I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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