參數(shù)資料
型號(hào): PIC16F77
廠商: Microchip Technology Inc.
英文描述: 40-Pin 8-Bit CMOS FLASH Microcontrollers(40腳、8位CMOS 閃速微控制器)
中文描述: 40引腳8位CMOS閃存微控制器(40腳,8位的CMOS閃速微控制器)
文件頁數(shù): 17/170頁
文件大?。?/td> 3150K
代理商: PIC16F77
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 17
PIC16F7X
Bank 2
100h
(4)
101h
102h
(4)
103h
(4)
104h
(4)
105h
106h
107h
108h
109h
10Ah
(1,4)
PCLATH
10Bh
(4)
10Ch
10Dh
10Eh
10Fh
Bank 3
180h
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
TMR0
Timer0 Module
s Register
xxxx xxxx
uuuu uuuu
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
PORTB
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
xxxx xxxx
uuuu uuuu
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PMDATA
PMADR
PMDATH
PMADRH
Data Register Low Byte
Address Register Low Byte
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
Data Register High Byte
xxxx xxxx
uuuu uuuu
Address Register High Byte
xxxx xxxx
uuuu uuuu
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
0000 0000
181h
OPTION_
REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
182h
(4)
183h
(4)
184h
(4)
185h
186h
187h
188h
189h
18Ah
(1,4)
PCLATH
18Bh
(4)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
uuuu uuuu
TRISB
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
1111 1111
1111 1111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
---0 0000
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
18Ch
PMCON1
(6)
Unimplemented
Reserved maintain clear
Reserved maintain clear
RD
1--- ---0
1--- ---0
18Dh
18Eh
18Fh
Legend:
x
= unknown,
u
= unchanged,
q
= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as
0
.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as
0
.
This bit always reads as a
1
.
0000 0000
0000 0000
0000 0000
0000 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
RESETS
(2)
Note 1:
2:
3:
4:
5:
6:
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