參數(shù)資料
型號: PIC16F77
廠商: Microchip Technology Inc.
英文描述: 40-Pin 8-Bit CMOS FLASH Microcontrollers(40腳、8位CMOS 閃速微控制器)
中文描述: 40引腳8位CMOS閃存微控制器(40腳,8位的CMOS閃速微控制器)
文件頁數(shù): 62/170頁
文件大?。?/td> 3150K
代理商: PIC16F77
PIC16F7X
DS30325A-page 62
Advance Information
2000 Microchip Technology Inc.
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP:
SPI Data Input Sample Phase
SPI Master mode:
1
= Input data sampled at end of data output time
0
= Input data sampled at middle of data output time (Microwire
)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I
2
C mode:
This bit must be maintained clear
CKE
: SPI Clock Edge Select (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode:
CKP = 0
1
= Data transmitted on rising edge of SCK (Microwire
alternate)
0
= Data transmitted on falling edge of SCK
CKP = 1
1
= Data transmitted on falling edge of SCK (Microwire
default)
0
= Data transmitted on rising edge of SCK
I
2
C mode:
This bit must be maintained clear
D/A
: Data/Address bit (I
2
C mode only)
1
= Indicates that the last byte received or transmitted was data
0
= Indicates that the last byte received or transmitted was address
P
: STOP bit (I
2
C mode only)
This bit is cleared when the SSP module is disabled, or when the START bit is detected last.
SSPEN is cleared.
1
= Indicates that a STOP bit has been detected last (this bit is
0
on RESET)
0
= STOP bit was not detected last
S
: START bit (I
2
C mode only)
This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last.
SSPEN is cleared.
1
= Indicates that a START bit has been detected last (this bit is
0
on RESET)
0
= START bit was not detected last
R/W
: Read/Write bit Information (I
2
C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or ACK bit.
1
= Read
0
= Write
UA
: Update Address (10-bit I
2
C mode only)
1
= Indicates that the user needs to update the address in the SSPADD register
0
= Address does not need to be updated
BF
: Buffer Full Status bit
Receive (SPI and I
2
C modes):
1
= Receive complete, SSPBUF is full
0
= Receive not complete, SSPBUF is empty
Transmit (I
2
C mode only):
1
= Transmit in progress, SSPBUF is full
0
= Transmit complete, SSPBUF is empty
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
1
= Bit is set
U = Unimplemented bit, read as
0
0
= Bit is cleared
x = Bit is unknown
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