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| 型號(hào)： | PIC16LC782T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 162/186頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 2KX14 A/D D/A 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲(chǔ)器容量： | 3.5KB（2K x 14） |
| 程序存儲(chǔ)器類(lèi)型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b; D/A 1x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱(chēng)： | PIC16LC782TI/SS |
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2001 Microchip Technology Inc.
Preliminary
DS41171A-page 75
PIC16C781/782
9.4.1
FASTER CONVERSION/LOWER
RESOLUTION TRADE-OFF
Not all applications require a result having 8-bits of res-
olution. Some may instead, require a faster conversion
time. The ADC module allows users to make a trade-off
of conversion speed for resolution. Regardless of the
resolution required, the acquisition time is the same. To
speed up the conversion, the clock source of the ADC
module may be switched during the conversion, so that
the TAD time violates the minimum specified time (see
the applicable Electrical Specification). Once the switch
is made, all the following ADC result bits are invalid
(see ADC Conversion Timing in the Electrical Specifi-
cations section). The clock source may only be
switched between the three oscillator options (it cannot
be switched from/to RC). The equation to determine
the time before the oscillator must be switched for a
desired resolution is as follows:
Conversion time = 2TAD + N TAD + (8 - N)(2TOSC)
Where: N = number of bits of resolution required.
Since the TAD is based on the device oscillator, the user
must employ some method (such as a timer, software
loop, etc.) to determine when the ADC oscillator must
be changed.
9.5
ADC Operation During SLEEP
The ADC module can operate during SLEEP mode.
This requires that the ADC clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the ADC module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit is cleared, and the
result is loaded into the ADRES register. If the ADC
interrupt is enabled, the device awakens from SLEEP.
If the ADC interrupt is not enabled, the ADC module is
turned off, although the ADON bit remains set.
When the ADC clock source is another clock option
(not RC), a SLEEP instruction causes the present con-
version to be aborted and the ADC module to be turned
off. The ADON bit remains set.
Turning off the ADC places the ADC module in its low-
est current consumption state.
9.6
ADC Accuracy/Error
The absolute accuracy (absolute error) specified for the
ADC converter includes the sum of all contributions for:
Offset error
Gain error
Quantization error
Integral non-linearity error
Differential non-linearity error
Monotonicity
The absolute error is defined as the maximum devia-
tion from an actual transition versus an ideal transition
for any code. The absolute error of the ADC converter
is specified as < ±1 LSb for ADCREF = VDD (over the
device’s specified operating range). However, the
accuracy of the ADC converter degrades as VDD
diverges from VREF.
For a given range of analog inputs, the output digital
code will be the same. This is due to the quantization of
the analog input to a digital code. Quantization error
is typically ± 1/2 LSb and is inherent in the analog to
digital conversion process. The only way to reduce
quantization error is to use an ADC with greater resolu-
tion of the ADC converter.
Offset error measures the first actual transition of a
code versus the first ideal transition of a code. Offset
error shifts the entire transfer function. Offset error can
be calibrated out of a system, or introduced into a sys-
tem, through the interaction of the total leakage current
and source impedance at the analog input.
Gain error measures the maximum deviation of the
last actual transition and the last ideal transition
adjusted for offset error. This error appears as a
change in slope of the transfer function. The difference
in gain error to full scale error is that full scale does not
take offset error into account. Gain error can be cali-
brated out in software.
Linearity error refers to the uniformity of the code
changes. Linearity errors cannot be calibrated out of
the system. Integral non-linearity error measures the
actual code transition versus the ideal code transition,
adjusted by the gain error for each code. Differential
non-linearity measures the maximum actual code
width versus the ideal code width. This measure is
unadjusted.
If the linearity errors are very large, the ADC may
become non-monotonic. This occurs when the digital
values for one or more input voltages are less than the
value for a lower input voltage.
Note:
For the ADC module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an ADC
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
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| PIC16LC923-04/L | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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| PIC16LC923-04I/L | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16LC923-04I/PT | 功能描述:8位微控制器 -MCU 7KB 176 RAM 52 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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