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參數(shù)資料
| 型號(hào)： | PIC16LC782T-I/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 29/186頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX14 A/D D/A 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,600 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲(chǔ)器容量： | 3.5KB（2K x 14） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b; D/A 1x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16LC782TI/SS |
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PIC16C781/782
DS41171A-page 122
Preliminary
2001 Microchip Technology Inc.
14.4
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when a
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, simply enable the internal
MCLR feature. This eliminates external RC compo-
nents usually needed to create a Power-on Reset. A
maximum
rise time for
VDD is
specified.
See
Section 17.0 for details. For a slow rise time, see
Two delay timers (PWRT on OST) are provided, which
hold the device in RESET after a POR (dependent
upon device configuration), so that all operational
parameters have been met prior to releasing the device
to resume/begin normal operation.
When the device starts normal operation (exits the
RESET condition), device operating parameters (i.e.,
voltage, frequency, temperature,...) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Brown-out Reset may be used to meet
the start-up conditions, or if necessary an external POR
circuit may be implemented to delay end of RESET for
as long as needed.
FIGURE 14-5:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD RAMP)
14.5
Power-up Timer (PWRT)
The Power-up Timer provides a fixed TPWRT time-out
on power-up type RESETS only. For a POR, the PWRT
is invoked when the POR pulse is generated. For a
BOR, the PWRT is invoked when the device exits the
RESET condition (VDD rises above BOR trip point).
The Power-up Timer operates on an internal RC oscil-
lator. The chip is kept in RESET as long as the PWRT
is active. The PWRT’s time delay is designed to allow
VDD to rise to an acceptable level. A configuration bit
(PWRT) is provided to enable/disable the PWRT for the
POR only. For a BOR the PWRT is always available
regardless of the configuration bit setting.
The power-up time delay varies from chip-to-chip due
to VDD, temperature and process variation. See DC
parameters for details.
14.6
Programmable Brown-out Reset
(PBOR)
The Programmable Brown-out Reset module is used to
generate a RESET when the supply voltage falls below
a specified trip voltage. The trip voltage is configurable
to any one of four voltages provided by the BORV<1:0>
configuration word bits.
Configuration bit BODEN can disable (if clear/pro-
grammed), or enable (if set), the Brown-out Reset cir-
cuitry. If VDD falls below the specified trip point for
Table 17-6), the brown-out situation resets the chip. A
RESET may not occur if VDD falls below the trip point
for less than TBOR. The chip remains in Brown-out
Reset until VDD rises above VBOR. The Power-up Timer
is invoked at that point and keeps the chip in RESET an
additional TPWRT. If VDD drops below VBOR while the
Power-up Timer is running, the chip goes back into a
Brown-out Reset and the Power-up Timer is re-
initialized. Once VDD rises above VBOR, the Power-up
Timer again begins a TPWRT time delay.
14.7
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked by the POR pulse.
When the PWRT delay expires, the Oscillator Start-up
Timer is activated. The total time-out varies depending
on oscillator configuration and the status of the PWRT.
For example, in RC mode with the PWRT disabled,
there is no time-out at all. Figure 14-6, and Figure 14-9
depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs expire. Then,
bringing MCLR high begins execution immediately.
This is useful for testing purposes or to synchronize
more than one PICmicro microcontroller operating in
parallel.
Table 14-5 shows the RESET conditions for some spe-
cial function registers.
Note
1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor quickly
when VDD powers down.
2: R < 40 k
is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100
to 1 k will limit any current flow-
ing into MCLR from external capacitor C in
the event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16C781/782
VDD
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