參數資料
型號: PIC17C756A-16I/L
廠商: Microchip Technology
文件頁數: 114/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D PWM 68PLCC
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 19
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 50
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數據轉換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
配用: AC164308-ND - MODULE SKT FOR PM3 68PLCC
DVA17XL681-ND - DEVICE ADAPTER FOR PIC17C752
DM173001-ND - KIT DEVELOPMENT PICDEM17
AC174007-ND - MODULE SKT PROMATEII 68PLCC
AC164024-ND - ADAPTER PICSTART PLUS 68PLCC
2000 Microchip Technology Inc.
DS30289B-page 57
PIC17C7XX
7.8
Bank Select Register (BSR)
The BSR is used to switch between banks in the data
memory area (Figure 7-9). In the PIC17C7XX devices,
the entire byte is implemented. The lower nibble is
used to select the peripheral register bank. The upper
nibble is used to select the general purpose memory
bank.
All the Special Function Registers (SFRs) are mapped
into the data memory space. In order to accommodate
the large number of registers, a banking scheme has
been used. A segment of the SFRs, from address 10h
to address 17h, is banked. The lower nibble of the bank
select register (BSR) selects the currently active
“peripheral bank.” Effort has been made to group the
peripheral registers of related functionality in one bank.
However, it will still be necessary to switch from bank to
bank in order to address all peripherals related to a sin-
gle task. To assist this, a MOVLB bank instruction has
been included in the instruction set.
The need for a large general purpose memory space
dictated a general purpose RAM banking scheme. The
upper nibble of the BSR selects the currently active
general purpose RAM bank. To assist this, a MOVLR
bank
instruction has been provided in the instruction
set.
If the currently selected bank is not implemented (such
as Bank 13), any read will read all '0's. Any write is
completed to the bit bucket and the ALU status bits will
be set/cleared as appropriate.
FIGURE 7-9:
BSR OPERATION
Note:
Registers in Bank 15 in the Special Func-
tion Register area, are reserved for
Microchip use. Reading of registers in this
bank may cause random values to be read.
74 3
0
10h
17h
BSR
0
1
2
3
8
15
20h
FFh
(1)
(2)
Bank 15
Bank 8
Bank 3
Bank 2
Bank 1
Bank 0
01
2
Bank 2
Bank 1
Bank 0
15
Bank 15
SFR
Banks
GPR
Banks
Address
Range
Note
1:
For the SFRs only Banks 0 through 8 are implemented. Selection of an unimplemented bank is not recommended.
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.
2: For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank
is not recommended.
3: SFR Bank 8 is only implemented on the PIC17C76X.
3
Bank 3
4
Bank 4
4
5
6
7
Bank 7
Bank 6
Bank 5
Bank 4
(Peripheral)
(RAM)
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