2000 Microchip Technology Inc.
DS30289B-page 43
PIC17C7XX
7.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC17C7XX; pro-
gram memory and data memory. Each block has its
own bus, so that access to each block can occur during
the same oscillator cycle.
The data memory can further be broken down into
General Purpose RAM and the Special Function Reg-
isters (SFRs). The operation of the SFRs that control
the “core” are described here. The SFRs used to con-
trol the peripheral modules are described in the section
discussing each individual peripheral module.
7.1
Program Memory Organization
PIC17C7XX devices have a 16-bit program counter
capable of addressing a 64K x 16 program memory
space. The RESET vector is at 0000h and the interrupt
vectors are at 0008h, 0010h, 0018h, and 0020h
7.1.1
PROGRAM MEMORY OPERATION
The PIC17C7XX can operate in one of four possible
program memory configurations. The configuration is
selected by configuration bits. The possible modes are:
Microprocessor
Microcontroller
Extended Microcontroller
Protected Microcontroller
The Microcontroller and Protected Microcontroller
modes only allow internal execution. Any access
beyond the program memory reads unknown data. The
Protected Microcontroller mode also enables the code
protection feature.
The Extended Microcontroller mode accesses both
the internal program memory, as well as external pro-
gram
memory.
Execution
automatically
switches
between internal and external memory. The 16-bits of
address allow a program memory range of 64K-words.
The Microprocessor mode only accesses the external
program memory. The on-chip program memory is
ignored. The 16-bits of address allow a program mem-
ory range of 64K-words. Microprocessor mode is the
default mode of an unprogrammed device.
The different modes allow different access to the con-
figuration bits, test memory and boot ROM.
Table 7-1lists which modes can access which areas in memory.
Test Memory and Boot Memory are not required for
normal operation of the device. Care should be taken
to ensure that no unintended branches occur to these
areas.
FIGURE 7-1:
PROGRAM MEMORY MAP
AND STACK
PC<15:0>
Stack Level 1
Stack Level 16
RESET Vector
INT Pin Interrupt Vector
Timer0 Interrupt Vector
T0CKI Pin Interrupt Vector
Peripheral Interrupt Vector
FOSC0
FOSC1
WDTPS0
WDTPS1
PM0
Reserved
PM1
Reserved
C
onf
igurat
ion
M
e
mory
Sp
a
c
e
Us
er
Mem
o
ry
Sp
a
c
e
(1
)
CALL, RETURN
RETFIE, RETLW
16
0000h
0008h
0010h
0020h
0021h
0018h
FDFFh
FE00h
FE01h
FE02h
FE03h
FE04h
FE05h
FE06h
FE07h
FE0Fh
Test EPROM
Boot ROM
FE10h
FF5Fh
FF60h
FFFFh
1FFFh
3FFFh
(PIC17C752
(PIC17C756A
Reserved
PM2
FE08h
Note
1:
User memory space may be internal, external,
or both. The memory configuration depends
on the processor mode.
FE0Eh
BODEN
FE0Dh
PIC17C762)
PIC17C766)