參數(shù)資料
型號: PIC17C756A-16I/L
廠商: Microchip Technology
文件頁數(shù): 28/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D PWM 68PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 19
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 50
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-LCC(J 形引線)
包裝: 管件
配用: AC164308-ND - MODULE SKT FOR PM3 68PLCC
DVA17XL681-ND - DEVICE ADAPTER FOR PIC17C752
DM173001-ND - KIT DEVELOPMENT PICDEM17
AC174007-ND - MODULE SKT PROMATEII 68PLCC
AC164024-ND - ADAPTER PICSTART PLUS 68PLCC
Section 4 Clock Pulse Generator (CPG)
R01UH0025EJ0300 Rev. 3.00
Page 91 of 1336
Sep 24, 2010
SH7261 Group
4.5
Changing the Frequency
The frequency of the CPU clock (I
φ) and peripheral clock (Pφ) can be changed either by changing
the multiplication rate of PLL circuit 1 or by changing the division rates of divider. All of these
are controlled by software through the frequency control register (FRQCR). The methods are
described below.
4.5.1
Changing the Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1 time.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
WDT. The following must be set:
WTCSR.TME
= 0: WDT stops
WTCSR.CKS[2:0]: Division ratio of WDT count clock
WTCNT counter: Initial counter value
3. Set the desired value in the STC[2:0] bits. The division ratio can also be set in the IFC[2:0] and
PFC[2:0] bits.
4. This LSI pauses temporarily and the WDT starts incrementing. The CPU and peripheral clocks
both stop and the WDT is supplied with the clock. The clock will continue to be output at the
CKIO pin. This state is the same as software standby mode. Whether or not registers are
initialized depends on the module. For details, see section 27, Power-Down Modes.
5. Supply of the clock that has been set begins at WDT count overflow, and this LSI begins
operating again. The WDT stops after it overflows.
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