參數(shù)資料
型號： PIC18F45J50-I/PT
廠商： Microchip Technology
文件頁數(shù)： 118/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓(xùn)模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 160
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 57
PIC18F46J50 FAMILY
4.6.9
DEEP SLEEP MODE REGISTERS
Deep Sleep mode registers are provided
in
REGISTER 4-1:
DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh)
R/W-0
U-0
R/W-0
DSEN(1)
—
r
DSULPEN
RTCWDIS
bit 7
bit 0
Legend:
r = Reserved bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSEN:
Deep Sleep Enable bit(1)
1
= Deep Sleep mode is entered on a SLEEP command
0
= Sleep mode is entered on a SLEEP command
bit 6-3
Unimplemented:
Read as ‘0’
bit 2
Reserved:
Always write ‘0’ to this bit
bit 1
DSULPEN:
Ultra Low-Power Wake-up Module Enable bit
1
= ULPWU module is enabled in Deep Sleep
0
= ULPWU module is disabled in Deep Sleep
bit 0
RTCWDIS:
RTCC Wake-up Disable bit
1
= Wake-up from RTCC is disabled
0
= Wake-up from RTCC is enabled
Note 1:
In order to enter Deep Sleep, Sleep must be executed immediately after setting DSEN.
REGISTER 4-2:
DSCONL: DEEP SLEEP CONTROL LOW BYTE REGISTER (BANKED F4Ch)
U-0
R/W-0
R/W-0(1)
—
ULPWDIS
DSBOR
RELEASE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented:
Read as ‘0’
bit 2
ULPWDIS:
Ultra Low-Power Wake-up Disable bit
1
= ULPWU wake-up source is disabled
0
= ULPWU wake-up source is enabled (must also set DSULPEN = 1)
bit 1
DSBOR:
Deep Sleep BOR Event Status bit
1
= DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep,
but did not fall below VDSBOR
0
= DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep
bit 0
RELEASE:
I/O Pin State Release bit
Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will
release the I/O pins and allow their respective TRIS and LAT bits to control their states.
Note 1:
This is the value when VDD is initially applied.
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