參數(shù)資料
型號: PIC18F45J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 158/164頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 93
PIC18F46J50 FAMILY
SSP2CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
GCEN
ACKSTAT
ADMSK5(4) ADMSK4(4)
ADMSK3(4)
ADMSK2(4)
ADMSK1(4)
SEN
CMSTAT
COUT2
COUT1
---- --11
PMADDRH/
CS1
Parallel Master Port Address High Byte
-000 0000
PMDOUT1H(5,6) Parallel Port Out Data High Byte (Buffer 1)
0000 0000
PMADDRL/
Parallel Master Port Address Low Byte
0000 0000
PMDOUT1L(5,6) Parallel Port Out Data Low Byte (Buffer 0)
0000 0000
PMDIN1H(5)
Parallel Port In Data High Byte (Buffer 1)
0000 0000
PMDIN1L(5)
Parallel Port In Data Low Byte (Buffer 0)
0000 0000
TXADDRL
SPI DMA Transit Data Pointer Low Byte
xxxx xxxx
TXADDRH
SPI DMA Transit Data Pointer High Byte
---- xxxx
RXADDRL
SPI DMA Receive Data Pointer Low Byte
xxxx xxxx
RXADDRH
SPI DMA Receive Data Pointer High Byte
---- xxxx
DMABCL
SPI DMA Byte Count Low Byte
xxxx xxxx
DMABCH
SPI DMA Byte Count High
Byte
---- --xx
UCON
PPBRST
SE0
PKTDIS
USBEN
RESUME
SUSPND
-0x0 000-
USTAT
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI
-xxx xxx-
UEIR
BTSEF
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
0--0 0000
UIR
SOFIF
STALLIF
IDLEIF
TRNIF
ACTVIF
UERRIF
URSTIF
-000 0000
UFRMH
—FRM10
FRM9
FRM8
---- -xxx
UFRML
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
xxxx xxxx
PMCONH(5)
PMPEN
ADRMUX1
ADRMUX0
PTBEEN
PTWREN
PTRDEN
0--0 0000
PMCONL(5)
CSF1
CSF0
ALP
CS1P
BEP
WRSP
RDSP
000- 0000
PMMODEH(5)
BUSY
IRQM1
IRQM0
INCM1
INCM0
MODE16
MODE1
MODE0
0000 0000
PMMODEL(5)
WAITB1
WAITB0
WAITM3
WAITM2
WAITM1
WAITM0
WAITE1
WAITE0
0000 0000
PMDOUT2H(5) Parallel Port Out Data High Byte (Buffer 3)
0000 0000
PMDOUT2L(5) Parallel Port Out Data Low Byte (Buffer 2)
0000 0000
PMDIN2H(5)
Parallel Port In Data High Byte (Buffer 3)
0000 0000
PMDIN2L(5)
Parallel Port In Data Low Byte (Buffer 2)
0000 0000
PMEH(5)
PTEN15
PTEN14
PTEN13
PTEN12
PTEN11
PTEN10
PTEN9
PTEN8
0000 0000
PMEL(5)
PTEN7
PTEN6
PTEN5
PTEN4
PTEN3
PTEN2
PTEN1
PTEN0
0000 0000
PMSTATH(5)
IBF
IBOV
IB3F
IB2F
IB1F
IB0F
00-- 0000
PMSTATL(5)
OBE
OBUF
OB3E
OB2E
OB1E
OB0E
10-- 1111
CVRCON
CVREN
CVROE
CVRR
r
CVR3
CVR2
CVR1
CVR0
0000 0000
TCLKCON
—T1RUN
T3CCP2
T3CCP1
---0 --00
DSGPR1
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
uuuu uuuu
DSGPR0
Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep)
uuuu uuuu
DSCONH
DSEN
r
DSULPEN
RTCWDIS 0--- -000
DSCONL
ULPWDIS
DSBOR
RELEASE ---- -000
DSWAKEH
—DSINT0
---- ---0
DSWAKEL
DSFLT
DSULP
DSWDT
DSRTC
DSMCLR
DSPOR
0-00 00-1
TABLE 6-4:
REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on Page:
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note
1:
Bit 21 of the PC is only available in Serial Programming (SP) modes.
2:
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3:
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4:
Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See Section 19.5.3.2 “Address
Masking Modes”
for details.
5:
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6:
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7:
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
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