參數(shù)資料
型號： PIC18F45J50-I/PT
廠商： Microchip Technology
文件頁數(shù)： 97/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓(xùn)模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 160
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 43
PIC18F46J50 FAMILY
The use of the flag and control bits in the OSCCON
register is discussed in more detail in Section 4.0
.
3.5.2
OSCILLATOR TRANSITIONS
PIC18F46J50 family devices contain circuitry to
prevent clock “glitches” when switching between clock
sources. A short pause in the device clock occurs dur-
ing the clock switch. The length of this pause is the sum
of two cycles of the old clock source and three to four
cycles of the new clock source. This formula assumes
that the new clock source is stable.
Clock transitions are discussed in more detail in
.
Note 1:
The Timer1 crystal driver is enabled by
setting the T1OSCEN bit in the Timer1
Control register (T1CON<3>). If the
Timer1 oscillator is not enabled, then any
attempt to select the Timer1 clock source
will be ignored.
2:
If Timer1 is driving a crystal, it is recom-
mended that the Timer1 oscillator be
operating and stable prior to switching to
it as the clock source; otherwise, a very
long delay may occur while the Timer1
oscillator starts.
REGISTER 3-2:
OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h)
R/W-0
R/W-1
R/W-0
R-1(1)
U-1
R/W-0
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
—SCS1
SCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IDLEN:
Idle Enable bit
1
= Device enters Idle mode on SLEEP instruction
0
= Device enters Sleep mode on SLEEP instruction
bit 6-4
IRCF<2:0>:
Internal Oscillator Frequency Select bits
111
= 8 MHz (INTOSC drives clock directly)
110
= 4 MHz(2)
101
= 2 MHz
100
= 1 MHz
011
= 500 kHz
010
= 250 kHz
001
= 125 kHz
000
= 31 kHz (from either INTOSC/256 or INTRC directly)(3)
bit 3
OSTS:
Oscillator Start-up Time-out Status bit(1)
1
= Oscillator Start-up Timer time-out has expired; primary oscillator is running
0
= Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2
Unimplemented:
Read as ‘1’
bit 1-0
SCS<1:0>:
System Clock Select bits
11
= Postscaled internal clock (INTRC/INTOSC derived)
10
= Reserved
01
= Timer1 oscillator(4)
00
= Primary clock source (INTOSC postscaler output when FOSC<2:0> = 001 or 000)
00
= Primary clock source (CPU divider output for other values of FOSC<2:0>)
Note 1:
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
2:
Default output frequency of INTOSC on Reset (4 MHz).
3:
Source selected by the INTSRC bit (OSCTUNE<7>).
4:
Application firmware should first enable the Timer1 oscillator crystal driver by setting the T1OSCEN bit.
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