參數(shù)資料
型號： PIC18F45J50-I/PT
廠商： Microchip Technology
文件頁數(shù)： 21/164頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 32K 2V 44-TQFP
產(chǎn)品培訓模塊： XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 657 (CN2011-ZH PDF)
配用： AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2011 Microchip Technology Inc.
DS39931D-page 117
PIC18F46J50 FAMILY
9.1
INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
Note:
Interrupt flag bits are set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
REGISTER 9-1:
INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h)
R/W-0
R/W-x
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE/GIEH:
Global Interrupt Enable bit
When IPEN = 0:
1
= Enables all unmasked interrupts
0
= Disables all interrupts
When IPEN = 1:
1
= Enables all high-priority interrupts (also enables low-priority interrupts when GIEL is also set)
0
= Disables all interrupts
bit 6
PEIE/GIEL:
Peripheral/Low-Priority Interrupt Enable bit
When IPEN = 0:
1
= Enables all unmasked peripheral interrupts (when GIE is also set)
0
= Disables all peripheral interrupts
When IPEN = 1:
1
= Enables all interrupts configured for low priority (when GIEH is also set)
0
= Disables all interrupts configured for low priority
bit 5
TMR0IE:
TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 overflow interrupt
0
= Disables the TMR0 overflow interrupt
bit 4
INT0IE:
INT0 External Interrupt Enable bit
1
= Enables the INT0 external interrupt
0
= Disables the INT0 external interrupt
bit 3
RBIE:
RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2
TMR0IF:
TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
bit 1
INT0IF:
INT0 External Interrupt Flag bit
1
= The INT0 external interrupt occurred (must be cleared in software)
0
= The INT0 external interrupt did not occur
bit 0
RBIF:
RB Port Change Interrupt Flag bit(1)
1
= At least one of the RB<7:4> pins changed state (must be cleared in software)
0
= None of the RB<7:4> pins have changed state
Note 1:
A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch
condition and allow the bit to be cleared.
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