參數(shù)資料
型號(hào)： PIC18LF452T-I/L
廠商： Microchip Technology
文件頁數(shù)： 110/134頁
文件大?。?/td> 0K
描述： IC MCU FLASH 16KX16 A/D 44PLCC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 500
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 帶卷 (TR)
1997 Microchip Technology Inc.
DS30444E - page 77
PIC16C9XX
11.3.2
MASTER MODE
Master mode of operation is supported, in rmware,
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP and START bits will
toggle based on the start and stop conditions. Control
of the I2C bus may be taken when the P bit is set, or the
bus is idle with both the S and P bits clear.
In master mode the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
11.3.3
MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows the
determination of when the bus is free. The STOP (P)
and START (S) bits are cleared from a reset or when
the SSP module is disabled. The STOP and START bits
will toggle based on the start and stop conditions. Con-
trol of the I2C bus may be taken when bit P (SSP-
STAT<4>) is set, or the bus is idle with both the S and
P bits clear. When the bus is busy, enabling the SSP
Interrupt will generate the interrupt when the STOP
condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, they are:
Address Transfer
Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
TABLE 11-4: REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
LCDIF
ADIF(1)
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000
8Ch
PIE1
LCDIE
ADIE(1)
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
00-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000
87h
TRISC
—
PORTC Data Direction Control Register
--11 1111
Legend:
x
= unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by SSP in I2C mode.
Note
1: Bits ADIE and ADIF are reserved on the PIC16C923, always maintain these bits clear.
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