參數(shù)資料
型號(hào): PIC18LF452T-I/L
廠商: Microchip Technology
文件頁數(shù): 53/134頁
文件大?。?/td> 0K
描述: IC MCU FLASH 16KX16 A/D 44PLCC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 500
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8864RMN
April 2012
25
M9999-043012-1.5
Soft Power-Down Mode
The soft power-down mode is entered by setting bit [4:3] =10 in register 14. When KSZ8864RMN is in this mode, all PLL
clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from current
soft power down mode to normal operation mode and internal reset will be issued to make all internal registers go to the
default values.
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit [4:3]
=11 in register 14. When KSZ8864RMN is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value
will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on
or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver
block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8864RMN can
automatically enabled the PHY power up to normal power state from power saving mode.
During this power saving mode, the host CPU can set bit [4:3] in register 14 to transit the current power saving mode to
any one of the other three power management operation modes.
Port-Based Power-Down Mode
In addition, the KSZ8864RMN features a per-port power down mode. To save power, a PHY port that is not in use can be
powered down by the port registers control 13 bit3, or MIIM PHY registers 0 bit11.
Functional Overview: Switch Core
Address Look-Up
The internal look-up table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information. The KSZ8864RMN is guaranteed to learn 1K addresses and distinguishes itself from a hash-
based look-up table which, depending upon the operating environment and probabilities, may not guarantee the absolute
number of addresses it can learn.
Learning
The internal look-up engine updates its table with a new entry if the following conditions are met:
The received packet’s source address (SA) does not exist in the look-up table.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted first to make room for the new entry.
Migration
The internal look-up engine also monitors whether a station is moved. If this occurs, it updates the table accordingly.
Migration happens when the following conditions are met:
The received packet’s SA is in the table but the associated source port information is different.
The received packet is good; the packet has no receiving errors and is of legal length.
The look-up engine will update the existing record in the table with the new source port information.
Aging
The look-up engine will update the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the look-up engine will remove the
record from the table. The look-up engine constantly performs the aging process and will continuously remove aging
records. The aging period is 300 +/- 75 seconds. This feature can be enabled or disabled through Register 3. See
“Register 3” section.
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